7 Replies Latest reply on Mar 7, 2015 8:52 AM by JoMe_264151

    CPU Interfacing Directly with Verilog Component

    userc_41727

      All the tutorials I can find have status and control registers as the go between for custom components.

         

      Is it possible to write and read directly from/to a register in a verilog component? If so how?

        • 1. Re: CPU Interfacing Directly with Verilog Component
          JoMe_264151

          Of course you can write to verilog registers. The only problem is to get their names.Look into Component Author Guide chapter 6.2. Best practice is to rename the something cryptic names by #defining them in the component's .h file with better / shorter names.

             

           

             

          Bob

          • 2. Re: CPU Interfacing Directly with Verilog Component
            userc_41727

            I placed a status register for my verilog component. The compiler is compaining it cannot reference the read function for it, even though it is there.

               

            Is there a problem with the compiler or is there a conflict of some kind? Attached is the project.

            • 3. Re: CPU Interfacing Directly with Verilog Component
              JoMe_264151

              Your status register is named DAC856x_Manager_Done_Reg and from that you may read with DAC856x_Manager_Done_Reg_Read()

                 

               

                 

              Bob

              • 4. Re: CPU Interfacing Directly with Verilog Component
                userc_41727

                The compiler is giving me an error saying that function does not exist.

                   

                Build error: undefined reference to `DAC856x_Manager_Done_Reg_Read'

                • 5. Re: CPU Interfacing Directly with Verilog Component
                  JoMe_264151

                  When you look into the file  DAC856x_Manager_Done_Reg.c  you can see that the component was optimized-out. the reason would be that your verilog part for DONE_OUT signal allows for that. I admit that it is not easy to test verilog.

                     

                   

                     

                  Bob

                  • 6. Re: CPU Interfacing Directly with Verilog Component
                    vidvc_264506

                     Hi,

                       

                    in this case the FITTER is problematic. I have tested ...

                       

                    a. published example as is .... without any digital logic between the Verilog output reg DONE_OUT and Status_Reg component => M0120 Build error - undefined reference to by FITTER elimated Status_Reg

                       

                    b. published example with one digital NOT component inserted between DONE_OUT and Status_Reg. Compiler OK + Fitter OK => only the signal is inverted by the NOT.

                       

                    c.  published example with two digital NOTs components in series inserted between DONE_OUT and Status_Reg. => M0120 Build error - undefined reference to by FITTER elimated Status_Reg

                       

                    Solution is here, change the schematics according to b. and change the signal evaluation - signal is inverted.

                       

                    What remains .... HOW TO STOP unvanted FITTER OPTIMALIZATION. At least for study and testing purposed.

                       

                    Regards,

                       

                    Viktor

                    • 7. Re: CPU Interfacing Directly with Verilog Component
                      JoMe_264151

                      I am afraid that your solution removes the symptom and not the cause.

                         

                      The Component Author guide clearly states that the way of creating is at first checking the component itself in a testing environment before it is used. I would suggest you to test your verilog-core component with some control and status registers to get hands on the bug you made. As a matter of fact: the optimizing-out of a component is done only when the component is without any useand can be replaced by a simple logic level or when the component's outputs are not connected to any further logic. I never fiddled araound with the fitter, but I am quite sure that your DONE output is clamped to a single logical value.

                         

                       

                         

                      Bob