Are you defining your new component as schematic? Then you should be able to just add the existing component to it.
No, the new component is in verilog, as stated above.
Silly me, stopped reading the subject too early :(
AFAIK you can only instantiate components that are itself defined in verilog. So look whether the one you need is (there must be a meaningful .v file).
You need to include this .v file into yours (or cypress.v if its a PSoC building block such as clocks or control regs) and then just instantiate the component. I did a quick search in the existing components, and many of them instatiate registers and clock blocks - but I did not find one the re-uses another component. But looking at them should show how its done.