7 Replies Latest reply on Mar 25, 2015 6:54 AM by Madhu Lakshmipathy

    DMA flags Basic doubt

    denny.mathew

       Hi i would lie to rest all the DMA Flag doubts that has been a bother for a while.

         
            
      • For writing to Slave Fifo ie FPGA to GPIF
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      A current thread DMA RDY flag shows logic high or logic low (when the Buffer is Full/Not Full) ?

         
            
      • For reading from  Slave Fifo ie GPIF to FPGA
      •    
         

      A current thread DMA RDY flag shows logic high or logic low (when the Buffer is Empty/NotEmpty)?

         

      Now regarding partial flags..

         
            
      • Can we use the partial flag to check the to- be- written GPIF socket( by FPGA) . If it is not asserted we can judge that there must be space to be written ..right?? is it essential that we need a DMA ready flag for starting a transfer..
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      "DMA_RDY" is actually a signal that is asserted when there is no DMA buffer available to satisfy the request."

         

      Is this a valid conclusion .

         

       

         

      utmost curiosity

         

      Denny

        • 1. Re: DMA flags Basic doubt
          Madhu Lakshmipathy

           Hi,

             

          For FPGA to GPIF (SlaveWrite):

             

          If flag is asserted, DMA Buffers are full inside FX3. So FPGA cannto write. If flag is de-asserted, write can be done.

             

          (Asserted means High if Flag is Active high. Asserted means Low if flag is active low)

             

          For GPIF to FPGA (SlaveRead):

             

          If flag is asserted, DMA Buffers are empty inside FX3. So FPGA cannot read. If flag is de-asserted, readcan be done.

             

          (Asserted means High if Flag is Active high. Asserted means Low if flag is active low)

             

          Your assumption that "DMA_RDY" is actually a signal that is asserted when there is no DMA buffer available to satisfy the request." is valid

             

          Regarding Partial Flags:

             

          For FPGA to GPIF: You can actually monitor the partial flag for starting the transfer (provided you call the CyU3PSMStart API after the DMA Channel is created and started (CyU3PDmaChannelCreate and CyU3PDmaChannelSetXfer)

             

          For GPIF to FPGA: There is a bug in Fx3 which makes it not possible to monitor the partial flag for beginning slave read. There is a dirty workaound for using partial flags alone. We recommend you to this workaround, only if are running short of pins and must avoid using the DMA Ready flag for starting the transfer, If, so please let us know. We will provide you the steps for the workaround for using the partial flag for starting the data transfer.

             

          If not, if you are OK with monitorng the DMA Ready flags for starting the data transfer, please proceed with it.

             

          Regards,

             

          -Madhu Sudhan

          • 2. Re: DMA flags Basic doubt
            user_413707516

            Hi Madhu,

               

            could you please provide this workaround, because due to lag of pins, we would like to use partial flags only instead of using both the full/empty and the partial flags.

               

             

               

            Regards

               

            Stefan

            • 3. Re: DMA flags Basic doubt
              Madhu Lakshmipathy

               Hi Stephen,

                 

              Please refer the attached doc for details and workaround.

                 

              Regards,

                 

              - Madhu Sudhan

              • 4. Re: DMA flags Basic doubt
                Madhu Lakshmipathy

                 Forgot to attach the doc.

                   

                Here it is

                • 5. Re: DMA flags Basic doubt
                  denny.mathew

                  Hi Madhu.

                     

                  This is a great piece of info. Thanks for saving a lot of time and pins..

                     

                  Denny

                  • 6. Re: DMA flags Basic doubt
                    user_413707516

                    Hi Madhu.

                       

                    Thank you for this information.

                       

                    Just a question for clarification:

                       

                    In the document there is a signal flow of the DMA_ready and the DMA_Watermark flag (p. 2). For event "B" it denotes that the DMA_ready flag (green signal) is "de-asserted". I'm not sure but I think here the DMA-ready flag is still "asserted", only the DMA_Watermark flag (red signal) is de-asserted.

                       

                    Is my observation correct?

                       

                     

                       

                    Regards,

                       

                    Stefan

                    • 7. Re: DMA flags Basic doubt
                      Madhu Lakshmipathy

                       Yes, You are right. That was a typo

                         

                      regards,

                         

                      - Madhu Sudhan