I don't see any part of your cpld code that you are driving the FIFOADR[1:0] pins.
As per your description I think CPLD hasn't read any data. How are you controlling the voltages on FIFOADR[1:0] pins?
Can you share your schematics?
Also in FX2LP firmware, you are suing only EP2 and EP6 and both are double buffered.This is not the valid buffer configuration.Refer datasheet for valid buffer configuration options.