1 Reply Latest reply on Apr 1, 2015 2:16 AM by vavc

    Flag problem of usb fifo in communication between 68013A and XC9572XL

    qi.wen

       Hello!

         

        I bulit a set of system, which has 68013A and XC9572XL, the communication between them is used slave fifo, and the flags is in index mode, so the flagb is full flag of all usb fifos and the flagc is empty flag.In firmware, the EP2 is set to 2X out buffer, and it's size is 512.When I sent 512 data from pc to cpld through EP2, the flagb and flagc is both high, when I sent 1024 data or sent 512 data twice, the the flag c is high, and the flagb is low, it means that the fifo of EP2 is full.Cpld is ready to receive the 512 data, when the usb fifo is full only, and stoped when the fifo is empty, but I found that the flag is still full, when the cpld received the 512 data over correctly, and new 512 data could not be sent to EP2 next time any more (Even if I reset EP2)using cyconsole.Is the firmware has problem or the cpld program.Thanks a lot! SOS!!

         

        there are my codes:

         

        /***************************************firmware*************************************/

         

       CPUCS = 0x10;                 // CLKSPD[1:0]=10, for 48MHz operation

         

       SYNCDELAY;

         

       IFCONFIG = 0x43;

         

       SYNCDELAY;

         

       EP2CFG = 0xA2;

         

       SYNCDELAY;

         

       EP4CFG = 0x02;

         

      SYNCDELAY;

         

       EP6CFG = 0xe2;

         

      SYNCDELAY;

         

       EP8CFG = 0x02;

         

      SYNCDELAY;

         

      FIFORESET = 0x80;    SYNCDELAY;          // activate NAK-ALL to avoid race conditions

         

      FIFORESET = 0x02;    SYNCDELAY;         // reset, FIFO 2

         

      FIFORESET = 0x04;    SYNCDELAY;         // reset, FIFO 4

         

      FIFORESET = 0x06;    SYNCDELAY;         // reset, FIFO 6

         

      FIFORESET = 0x08;    SYNCDELAY;         // reset, FIFO 8

         

      FIFORESET = 0x00;    SYNCDELAY;

         

      EP2FIFOCFG = 0x01;   SYNCDELAY;  

         

      EP2FIFOCFG = 0x11;   SYNCDELAY; 

         

      EP6FIFOCFG = 0x0D;   SYNCDELAY; 

         

      PINFLAGSAB = 0x00;   SYNCDELAY;         // FLAGB - Indexed 满标志低电平有效

         

      PINFLAGSCD = 0x00;   SYNCDELAY;

         

      FIFOPINPOLAR = 0x3C; SYNCDELAY;

         

      EP6AUTOINLENL = 0x00;  SYNCDELAY;

         

      EP6AUTOINLENH = 0x20;  SYNCDELAY;

         

      /**************************************************cpld*****************************************/

         

      always @(negedge clk)//clk=IFCLK

         

      begin

         

        if(!rst)

         

        begin

         

         present_state <= state_idel;

         

         count_clk <= 10'd0;

         

         slrd <= 1'b0;

         

         sloe <= 1'b0;

         

         config_done <= 1'b0;

         

         done_delay_cnt <= 3'd0;

         

         user_control_data <= 20'd0;

         

        end

         

        else

         

        begin

         

         case(present_state)

         

         state_idel :

         

         begin

         

           if((!usbfifo_full)&(usbfifo_empty))// if only full start 

         

           begin

         

             present_state <= state_read;

         

             slrd <= 1'b1;

         

             sloe <= 1'b1;

         

           end

         

           else if((!usbfifo_empty)&(usbfifo_full)) if only empty stop

         

           begin

         

             present_state <= state_idel;

         

             slrd <= 1'b0;

         

             sloe <= 1'b0;

         

           end

         

         end

         

         state_read :

         

         begin

         

           if(count_clk <= 10'd511) 

         

           begin

         

             count_clk <= count_clk + 1'b1;

         

             if(count_clk == 10'd511)

         

             begin

         

               slrd <= 1'b0;

         

               sloe <= 1'b0;

         

             end

         

             else

         

             begin

         

               slrd <= 1'b1;

         

               sloe <= 1'b1;

         

             end

         

             case(count_clk)

         

             0:

         

               user_control_data[15:0] <= fddata;

         

             1:

         

               user_control_data[19:16] <= fddata[3:0];

         

             endcase

         

           end

         

           else if(count_clk == 10'd512)

         

           begin

         

             count_clk <= 10'd0;

         

             config_done <= 1'b1;

         

             present_state <= state_delay;

         

           end

         

         end

         

         state_delay :

         

         begin

         

           if(done_delay_cnt<=3'd6)

         

             done_delay_cnt <= done_delay_cnt + 1'b1;

         

           else

         

           begin

         

             config_done <= 1'b0;

         

             done_delay_cnt <= 3'd0;

         

             present_state <= state_idel;

         

           end

         

         end

         

         default :

         

           present_state <= state_idel;

         

         endcase

         

       end

         

      end

        • 1. Re: Flag problem of usb fifo in communication between 68013A and XC9572XL
          vavc

           HI,

             

           

             

          I don't see any part of your cpld code that you are driving the FIFOADR[1:0] pins.

             

           

             

          As per your description I think CPLD hasn't read any data. How are you controlling the voltages on FIFOADR[1:0] pins?

             

           

             

          Can you share your schematics?

             

           

             

          Also in FX2LP firmware, you are suing only EP2 and EP6 and both are double buffered.This is not the valid buffer configuration.Refer datasheet for valid buffer configuration options.

             

           

             

          Regards,
          Vikas