And, the FPGA is driven by the GPIF clock on FX3. On the posedge the 8 bits output of FPGA changes, and on the negedge the GPIF reads the data.
I wonder how your verilog writes, In cyfxgpiftousb example DMA_RDY_TH0 signal does not work as a signal to notifiy your FPGA to write data, so I think the data lost may cause by PIB thread 0 not ready for read your FPGA still write data to PIB_SOCKET_0.
I suggest you use our Slave fifo example for your specific application use. Link: http://www.cypress.com/?rID=51581
If you have any further questions, please feel free to create a technical support case, our Cypress expert will be glad to help you.