13 Replies Latest reply on Apr 1, 2015 3:46 AM by helic_263931

    SPI & DMA problem



      I trying to get a SPISlave to tranfer data to  an array via DMA.


      It should be 2 byte per burst, with transfer count =2.Every burst need new request


      Unfortunately only the first data is transfer , the second data is left in SPIS Rxbuffer.


      The SPIMaster seem to be working .Tested with an ocsi, and the the RxBuffer not empty interupt seem to be working


      Anyone have any idea what going on?


      Attached is the Workspace bundle





        • 1. Re: SPI & DMA problem

          My guess: The DMA is faster than incoming SPI transfer. So what you see is that the DMA starts the transfer as soon as the first byte is in the RX buffer. Then it transfers two bytes, but only one is meaningful (since the SPI has not received more). Then the DMA finishes, and only then the second byte will be placed in the RX buffer.

          • 2. Re: SPI & DMA problem

            Perhaps my understanding is wrong, but should DMA transfer only occur when there is a request?


                DMA_RxChannel= DMA_1_DmaInitialize(DMA_RX_S_BYTES_PER_BURST,DMA_RX_S_REQUEST_PER_BURST,




            with DMA_RX_S_REQUEST_PER_BURST=1u




            So only when Rxbuffer is not empty will the DMA be trigger, then transfer the data, Rxbuffer empty, then wait for the next 2byte of data,

            • 3. Re: SPI & DMA problem

               You may be able to get some information from the example project for the PSoC5 in the PSoC creator workspace.


              File->Example Project.  Device Family PSoC 5Lp, keyword SPI Slave, project SPIS_Example.  It uses DMA to transfer items, and provides full source code and configuration information for the SPI block.


                It is only running the project at 2mhz clock, but I don't think that is an issue.

              • 4. Re: SPI & DMA problem

                Actually I  modified my project from the SPIS example from PSoc creator.in the original code the DMA is loop on itself with 1 byte burst data.


                In my project , the DMA should transfer 2byte for 2 transfer count and finish(trigering DMAdone_flag). But as mentioned before , doesn't work properly.


                Has anyone ideas?

                • 5. Re: SPI & DMA problem

                  OK, I had a depper look into your project and couldn't see that you did something very unusual.


                  Only thing - but this shouldn't matter in this case - is the flag "CY_DMA_DISABLE_TD" which allows to terminate a running DMA which you do not use.


                  To step further: Hopefully you have access to a logic analyzer. Check whether you really get two nrq signals for your transfers from the SPI-component to see if the problem is located there.





                  • 6. Re: SPI & DMA problem

                    A really low cost but very capable logic analyzer, just do a search on ebay


                    "saleae logic analyzer".




                    Compatible With Saleae USB Logic 24MHz 8Ch Logic Analyzer for ARM FPGA




                    Regards, Dana.

                    • 7. Re: SPI & DMA problem

                      Start your Cypress update-manager, there is a correction in the SPI module. Also look near end of document for a known issue.





                      • 8. Re: SPI & DMA problem

                        Each request executes one burst. When you define the DMA to transfer 2 bytes per burst, it will transfer 2 bytes per request. The DMA doesn't care whether the RX FIFO has data in it, it will just read.

                        • 9. Re: SPI & DMA problem

                          ...and the request for dma is connected to the Rx interrupt that fires when a 16-bit word is stored.





                          • 10. Re: SPI & DMA problem

                            Can you try with the Creator 3.1 SP2? The SPI master in there has a bugfix that looks like it could be your problem ("Updated the status register FIFO source signals when Data Bits are set greater than 8 bits. -- The FIFO signals connected to status register were taken from the wrong place. This can cause incorrect data to be transmitted when an interrupt appears. "


                            (Edit: skip that - I forgot that you are using the SPI slave. Probably I need some coffee, or some sleep)

                            • 11. Re: SPI & DMA problem

                              One guess: did you try to set the 'bytes per burst' to 1 and then the burst count on the channel to 2? Thats what the example in AN52705 is doing (and AN61102 as well)

                              • 12. Re: SPI & DMA problem

                                Still no cigar..I  set the the SPIS to trigger when Rx FIFO is full (8Bytes) and trigger the DMA continously untill all 8 bytes is transfer(raise DMA done interupt). ..The data rare still wrong,


                                What I notice is the RxFIFO full interupt will trigger everytime the program started, eventhough FIFO is empty.


                                Already updated the component, still same problem persist

                                • 13. Re: SPI & DMA problem

                                  Your DMA trigger was set to "level" when I looked - maybe set that to edge triggering?


                                  I'm wary of how to use the DMA to transfer a 16bit register (because that is what you have in your SPI). It must nit transfer two times from the same memory location, but needs to transfer 2 consecutive bytes and then start again from the same address. They way to do that seems to be to set "bytes per burst" to 1 and "burst count" to 2.