1 Reply Latest reply on Apr 8, 2015 6:46 AM by Madhu Lakshmipathy

    Slave FIFO loopback transfer - FX3 failed to send data to FPGA

    qinyi.wang

       Hi,

         

      I'm working with the FX3 DVK, following the application notes AN65974 to perform stream_in, stream_out and loopback transfer with my Xilinx FPGA. When performing stream_in and stream_out transfer, it seems quite ok.

         

       

         

      However, during loopback transfer, after transfer data out, when I was trying to read data back from bulk in endpoint, it shows that zero length data transfered. I tried to capture how each control signal data react from FPGA side during transfer. I found that sfter SLOE# and SLRD# were both asserted, no data came out from FX3, my FPGA did not recieve any data, flagc and flagd remained 1.

         

       

         

      How can I solve this problem?

         

       

         

      Regards,

         

      Zoe