1 Reply Latest reply on Apr 12, 2015 6:11 AM by user_14586677

    Implementing Algorithmic Delta-Sigma ADC using PSoC 5LP

    peli.fidelman

       Hi,

         

      I'm Trying to implement an algorithmic delta-sigma modulator using PSoC.  An algorithmic delta-sigma modulator is a first order delta-sigma modulator plus a S/H device. It divides the Analog to digital conversion to a few steps in order to reduce the necessary number of samples and should work for a medium resolution (8-12 bits), See left side of attachment.

         

      As A Modulator I Tried using Kees first Order delta-sigma modulator in the following link: 

         

      http://www.cypress.com/?app=forum&id=2492&rID=76867

         

       

         

      The modulator digital output works fine (I used a Counter to check), but when I use an ADC to sample the modulator  analog output (the output of the integrator) I can't make sense of it. I use the modulator settings with Vref=1.024 [V] so that the input voltages would be between 0.5*Vref and 1.5*Vref, so I expected the output voltage to change also symmetrically around Vref. In practice I see that when I Insert A voltage larger than Vref than the modulator output is always larger or equal to Vref. When I insert a voltage smaller than Vref than the output voltage is always smaller or equal to Vref.  Also, I noticed that the span of the integrator output is always smaller than the span of the modulator input. for example, if the input is 1.5V the modulator output only got as high as 1.3V.

         

      I think I can understand the reason for the smaller output span of the integrator if the "Integration Capacitor" is larger than the "Sampling Capacitor", but I can't figure out why the integrator Voltage isn't symmetric around Vref. Kees modulator Uses an SCBlock (from the analog primitives library). I can't find a good documentation for it, the  best thing I found was this graph from the PSoC 5 TRM:  http://www.cypress.com/?docID=46050    (page 308)

         

      See a copy of the graph in the left side of the attachment.

         

      I don't fully understand the Configuration from the TRM. I get the (C2+C4+C5) is the Integration Capacitor and C1 is the Sampling Capacitor, but what is C3 for?

         

      I would appreciate some help to understand the TRM Modulator configuration and why I get Odd Results when measuring the Analog voltage in the Modulator Integrator output.

         

       

         

      Thanks,  

         

             Peli