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Hi,
I'm Trying to implement an algorithmic delta-sigma modulator using PSoC. An algorithmic delta-sigma modulator is a first order delta-sigma modulator plus a S/H device. It divides the Analog to digital conversion to a few steps in order to reduce the necessary number of samples and should work for a medium resolution (8-12 bits), See left side of attachment.
As A Modulator I Tried using Kees first Order delta-sigma modulator in the following link:
http://www.cypress.com/?app=forum&id=2492&rID=76867
The modulator digital output works fine (I used a Counter to check), but when I use an ADC to sample the modulator analog output (the output of the integrator) I can't make sense of it. I use the modulator settings with Vref=1.024
I think I can understand the reason for the smaller output span of the integrator if the "Integration Capacitor" is larger than the "Sampling Capacitor", but I can't figure out why the integrator Voltage isn't symmetric around Vref. Kees modulator Uses an SCBlock (from the analog primitives library). I can't find a good documentation for it, the best thing I found was this graph from the PSoC 5 TRM: http://www.cypress.com/?docID=46050 (page 308)
See a copy of the graph in the left side of the attachment.
I don't fully understand the Configuration from the TRM. I get the (C2+C4+C5) is the Integration Capacitor and C1 is the Sampling Capacitor, but what is C3 for?
I would appreciate some help to understand the TRM Modulator configuration and why I get Odd Results when measuring the Analog voltage in the Modulator Integrator output.
Thanks,
Peli
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PSoC 5LP
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You might try kees@cypress.com, if you are able to get the
info consider posting answer back to forum.
You could also file a CASE -
To create a technical or issue case at Cypress -
“Support”
“Technical Support”
“Create a Case”
You have to be registered on Cypress web site first.
Regards, Dana.