For one of our design, we want to use an FX3 and an FPGA to transfer data, in full duplex mode, between a PC and the FPGA. To test our configuration, I have linked a DE0-Nano board and an FX3 CYUSB3Kit-003 together.
I have used the FPGA code from the AN65974 (loopback) and modified the io assignment file to match our needs. I also have used the FX3 code from the same application note and changed CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT to 0, in order to match a 16 bits data bus length. A logic analyzer is hooked to the control signals (clock, slcs, slrd, slwr, sloe) and the status signals (flaga, flagb, flagc, flagd). The control signals seems correct but the flags are always stuck to '0'.
While using the USB Control Center, I was able to issue two write transfer from the USB to the FPGA. All the following transfers failed with the error code 997. I have the exact same error while trying to read fata from the FPGA to the USB.
Have you made some modifications in order to use the example code ?
trace.png 32.2 K
There is one more modification needed to be done in the firmware when using 16 bit GPIF.
In the cyfxslfifosync.c file, between the CyU3PGpifLoad and CyU3PGpifSMStart APIs, modify the existing code as:
#if (CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT == 0)
#else if (CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT == 1)
This configures the watermark flags properly for 16 bit data bus designs. This code will be included in the next release of An65974
- Madhu Sudhan
Thank you for your quick reply. Unfortunately it doesn't work better with the patch you gave me. I will try to investigate further and post my progress.
Just to be sure:
* FLAGA and FLAGB are linked to thread 0. This thread is used for transferring data
from the FPGA to the USB
* FLAGC and FLAGD are related to thread 3. This thread is used for moving data
from USB to FPGA
According to the definition of these flags, we can deduce that:
* FLAGA is asserted (logic '0') when the fifo in the FX3 is full
* FLAGB is asserted (logic '0') when the fifo in the FX3 contains more data than the threshold
* FLAGC is asserted (logic '0') when the fifo in the FX3 is empty
* FLAGD is asserted (logic '0') when the fifo in the FX3 contains less data than the threshold
Assuming the SLCS signal is always set to '0', to be able to read the flags values during a
READ transfer, the address to use is "11" and the signal SLRD must be set to '0'. After two clock
cycles, the flags are updated to match the socket status.
In order to do the same in a WRITE transfer, the address to use is "00" and the signal SLWR must be set to '0'.
Three clock cycles after, the flags can be read to see whether data can be pushed to the FX3 or not.
There should be atlease one clock cycle in which the address lines are 11 and SLRD is de-asserted (high). This leads to the IN_ADDR state where the address 11 is sampled. Only after this the flags for slaveread get updated and then you should assert SLRD (0) for starting the read.