It would help if you could post the project for the forum to
look at the entire resource demand and other issues like
“Create Workspace Bundle”
There was a similar discussion a while ago. Are you sing Half-duplex by any chance? The problem here might be again that the number of PTerms needed cannot be fit into the UDBs - the number of connections for that is then to big.
The UDB component is actually the same for all PSoC parts, thats why there are no special precautions for PSoC4 with limited resources. (btw: the upcoming 4200L series has 8 UDBs - see the roadmap)
Yes, per datasheet resources are exceeded -
Parts coming in Fall timeframe with 8 UDBs -
If I disable the "Hardware detect to buffer" feature it fits in a CY8C4245, but if I switch to "Half Duplex", which should use less resources, the creation process fails (E2071: Unable to pack the design into 4 UDBs). It doesn't matter if "Hardware TX-Enable" is used or not.
Could it be that there is something wrong with the v2.40 UART component?
Consider filing a CASE and posting back to forum answer -
To create a technical or issue case at Cypress -
“Create a Case”
You have to be registered on Cypress web site first.
The Half-Duplex version needs less UDB/Datapath resources, right. But since it switches, during runtime, the functionality of them between send and receive, the logic it uses internally is more complicates. And for that a too large number of combinatorical terms is needed.
It seems Cypress needs to rework this implementation, so a Support case should be the next step. (The component is not defective as such on the PSoC4, the same problem can happen on a PSoC5 although there the larger number UDBs defers the problem somewhat)