6 Replies Latest reply on Apr 21, 2015 6:12 AM by user_14586677

    Low Power Timer/Counter with Compare

    hardy.griech

      Hi,

         

      is it possible to wire the PSoC4BLE in a way, that the fixed Timer/Counters are running with LFCLK?

         

      Background: I need a (really) low power timer running at 4096Hz with a compare unit which is interrupt capable.

         

      My current efforts are always stuck, because PSoC Creator is telling me, that I have to use HFCLK as clock source, actually: "The component requires a clock from the clock block." So the question could be transformed to "how to put LFCLK into the clock block?"

         

      Thanks

         

      Hardy

        • 1. Re: Low Power Timer/Counter with Compare
          user_14586677

          Two possibilities -

             

           

             

          1) Use WDT with an ISR

             

           

             

             

           

             

          2) Use SysTick in lieu of WDT.

             

           

             

              

             

                   

             

          http://www.cypress.com/?id=4&rID=94607     PSOC 4 Systick

             

          http://www.cypress.com/?docID=49253     AN90799 (Systick as well)

             

           

             

          In either of these cases since timer is running so slow why not just use WDT

             

          or SysTick ISR and do the timing/counting/compare in software ?

             

           

             

           

             

           

             

          One last possibility, in this ap note www.google.com/url it states -

             

           

             

          Using HFCLK as the source, internal prescalers and dividers generate clocks for the ARM Cortex-M0 core, analog modules,and digital modules. LFCLK is directly used to drive the watchdog timer (WDT). If necessary, you can output LFCLK and SYSCLK (see Figure 4) via the PSoC 4100/4200 I/O pins (except Port 4).

             

           

             

          Unless someone else knows how to do this route file a CASE and ask for solution, post back

             

          here for all to see and use.

             

           

             

              

             

                   

             

          To create a technical or issue case at Cypress -

             

           

             

          www.cypress.com

             

          “Support”

             

          “Technical Support”

             

          “Create a Case”

             

           

             

          You have to be registered on Cypress web site first.

             

           

             

          Regards, Dana.

          • 3. Re: Low Power Timer/Counter with Compare
            hardy.griech

            Thanks Dana for your suggestions.

               

            Unfortunately not exactly what I'm looking for. I need a timer with some relatively high resolution (4096Hz, better 8192Hz). Interrupts should not be generated on this short period to avoid unnecessary µC load.

               

            Actually the timer is for some sort of "OS" but should not be periodic. It should be dynamic to allow long sleep periods of the processor.

               

            So I'm looking obvisouly for a way to route the LFCLK into the clocking scheme to allow connection to the fixed timer/counter. Any further ideas?

               

            Thanks & regards

               

            Hardy

            • 4. Re: Low Power Timer/Counter with Compare
              hardy.griech

              Ah yes, forgot a requirement: the timer should not loose ticks!

                 

              Hardy

              • 5. Re: Low Power Timer/Counter with Compare
                user_14586677

                Are you going to run this part in sleep or always active with HFCLK

                   

                running. If later what speed will your HFCLK be ?

                   

                 

                   

                Your target resolution is ~ 100 uS period into the timer. The part at

                   

                48 Mhz run~ 43 DMIPS.

                   

                 

                   

                Try a simple test with an ISR and some other process and compare

                   

                CPU loading, there might be enough horsepower to accomplish

                   

                what you are looking for.

                   

                 

                   

                 

                   

                 

                   

                Regards, Dana.

                • 6. Re: Low Power Timer/Counter with Compare
                  hardy.griech

                  Problem is that the device should almost always sleep except during some very short periods. This is because the application is battery driven. Average CPU load is about 1%.

                     

                  So leaving IMO/HFCLK on is no option. Also a fast periodic timer interrupt is not really one - actually I hate it to have fast periodic interrupts which are doing actually nothing then just checking that there is no work to be done... (sometimes I'm a purist)

                     

                  Current implementation is done with an MSP430 (if one might say this word in this forum...) with a capture/compare unit running at 32768Hz. And this is really low power!

                     

                  I will have a deeper look into SysTick.

                     

                  Nevertheless I'm open to more suggestions ;-)

                     

                  Hardy

                  • 7. Re: Low Power Timer/Counter with Compare
                    hardy.griech

                    Some results of my findings:

                       
                          
                    • using SysTick ist not the way, because it requires SYSCLK/HFCLK which is contradictionary to deep sleep.
                      Instead SysTick might be used to measure active phases of the µC for battery charge calculation

                       
                    •     
                    • watchdog seems the way to go. I've found a KB article about it: http://www.cypress.com/?id=4&rID=94605
                      But to be honest, I'm not really happy with the information contained. Hardware description is a little bit raw
                      Also functionality seems to be a little bit limited: no prescaler, no interrupt on wrap around, only one counter with compare capability if one needs the other WDT for actual watchdog functionality
                    •    
                       

                    I'm really wondering why it is not possible/forseen to source the fixed function blocks with LFCLK... little bit disappointing...

                       

                    Hardy

                    • 8. Re: Low Power Timer/Counter with Compare
                      user_14586677

                      Try filing a CASE, point to this thread, and post back what results

                         

                      you get.

                         

                       

                         

                          

                         

                                

                         

                      To create a technical or issue case at Cypress -

                         

                       

                         

                      www.cypress.com

                         

                      “Support”

                         

                      “Technical Support”

                         

                      “Create a Case”

                         

                       

                         

                      You have to be registered on Cypress web site first.

                         

                       

                         

                      Regards, Dana.