Look at digital block clock frequency specs, its a f() of component type
as well as gate level limitations. In the case of the latter looks like
49.2 Mhz in the case of raw clock chaining frequency on the input
side. But one cannot assume this would be chaining out.
You might want to confirm this by filing a CASE -
To create a technical or issue case at Cypress -
“Create a Case”
You have to be registered on Cypress web site first.