2 Replies Latest reply on Jun 12, 2015 8:10 AM by jake.wegman





      In the TRM, it mentions that one can access the FX3 internal MMIO space by use of three registers, PP_MMIO_ADDR, PP_MMIO_DATA, and PP_MMIO (which is a control register).  However, I cannot create the behavior that is outlined in the TRM.  Here's my code:



      ... #include "pib_regs.h" ...     for (curAddr = firstAddr; curAddr < lastAddr; curAddr += 4)     {         PIB->pp_mmio_addr = curAddr;         while ((PIB->pp_mmio & CY_U3P_PIB_MMIO_BUSY) > 0);         PIB->pp_mmio |= CY_U3P_PIB_MMIO_RD;         while ((PIB->pp_mmio & CY_U3P_PIB_MMIO_BUSY) > 0);         buffer[i] = PIB->pp_mmio_data;         i += 4;     } ... 

      If I place debug prints into the code, I see that all of the MMIO registers are always 0 (address, control, and data).  If I query PIB->config, I can see that the PP_MMIO protocol is enabled.  Does anybody know how this is supposed to work and why my code above does not perform as expected?