At first: you do not need to "compare" your signals, just write an equation like X = A & B; then you may take X as input for your (suggested) shift register.
Without wanting to spoil what you are working on:
Why don't you
Take two digital input pins and name them "A" and "B"
route the pins to the inputs of an AND
route the output of the AND to a shift-register, 8 bits wide with properties for shift in and a store-signal.
Drop a 4-bit counter component (under Digital->Utility) and generate a store-signal after 8 shift clocks
Write an interrupt handler that transfers the Shiftreg's fifo to UART (Later use DMA)
There is a Verilog manual already installed under Start->Cypress->PSoC Creator 3.2 ->Component Development Kit
And btw just to still my curiosity: Have you got a link to your used SAPD?
Thanks for your reply again. It must appear to you that I didn't take your prior suggestion... I apologize for that. Here I would like to mention that not only am I new to PSoC, I also have very little prior experience in working with electronics/ embedded systems. (I'm majoring in physics.) So something that may seem quite obvious to you might slip right above my head. I am as dumb as they come lol
Now I did go through the functions of Shift Register and I understand your suggestion about storing and data transfer. But my problem is this: The truth table I want isWhich means I do not want any output when A is 0. So I can't do that with just an AND gate you see! I probably need tristating here so I tried using a Bufoe but had no idea what to do with the feedback.Also since I am doing a physics experiment, we want to do many different kinds of analysis on the data. I only mentioned the most basic task above. We also want to check for repeating patterns etc. Of course we can do that after receivng the data on a computer but my task is to figure out how much of this analysis can be done on chip itself. So I am naturally curious about the possibility of designing customised UDB components.I have gone through the verilog manual. As I understand after verilog programming I have to do the datapath configuration. I went through the lectures here: http://www.cypress.com/?rID=48419 and I almost understand how to configure the datapath according to my verilog program except how to load input values into the accumulator. Apparently the accumulator can only be loaded from register or FIFO. And my input is through wires (net).Again, thank you for your patience with me!Regards
SAPD is Single Photon Avalance Diode.
So from your truth table I can see now that it is not an AND, but that you gate the signal with the A input.
Since you are getting a data stream I have to ask now if you need the information that there has been no result, which indeed would require a ternary logic. So "Do you gather any information in your resulting stream when A == 0" ?
"Do you only collect information when A == 1" ?
When searching for repeatitions in the stream, what do you estimate how far they may be apart?
Gating the datastream (no ternary logic) is not quite easy, but it works.
My intention to use ready made components (LUT, shift register etc) is related to the fact that the verilog is quite untestable, no debugging on an UDB, only go / no go. So when you have got a working example written with the (testable) components you may start to replace part of the logic with self-made verilogs.
Oh I see. The SPAD I use for my work is probably fabricated by my research group. I do not know much about it, only the pulse width, count rate, quenching period etc.
I do not store any information when A == 0. I only collect the value of B when A == 1. Since the signals are basically generated from single photons from a pulsed laser and/or SPDC source, because of the probabilistic (quantum) nature I do not know when a signal will be received (1 means signal received). The data generation will therefore be asynchronous.
The repetations in the output sequence will depend upon the bias in my laser/ beam splitter. I realize why you want such an estimate but I do not have a number with me now. It's a later part of my project and I shall have to discuss with my advisor and do a quantitative formulation. If you can suggest a way to realize the first task, as I described above, using ready made components then it's be very helpful for now.
I understand that verilog components are untestable by psoc creator, so I am planning to test a known sequance of signals once the component is ready. I feel like I have almost configured a UDB component to do the above task with some simple logic, store the sequence as bytes in FIFO and transfer using DMA, except I am stuck in datapath config: I do not know how to load input signals into A0 and A1 :(
Off-topic: I see this discussion under different angle. Your major is in physics, not in EE, you might be waisting your time on issues unrelated to your future profession. Knowledge of Verilog or embedded programming will not contribute to your career. If, otherwise, you enjoy coding, you better switch to CS or EE now, while you are young - you will be better of in a long run- from personal experience there are not many jobs for physicists nowadays.
Most professors treat grad students as a cheap labor, and instead of outsourcing engineering work, they dump it on them - do not fall to this trap! Find a professional who skilled in PSoC and outsource problem. Ask on this forum or contact Cypress for professional support.
" I do not know how to load input signals into A0 and A1 :( " Since your signal is only one bit in width, your assumption to use the shift-in is quite right. Only way to make a byte out of that is a shift register.
I understand that verilog components are untestable by psoc creator,
Yes, there is not a simulator in Creator but you can write verilog for testability, with
test vectors, and watch pins, ports for output. Also on market there are simulators,
like Modelsim, that you could work with. The FPGA guys, like Xilinx and Altera, have
free versions of tools with sim you can download. And learning curve for basic stuff
not too bad, many training videos.
In PSOC Creator there is a LUT component that you can build state machines with,
w/o having to write verilog.
http://www.cypress.com/?rID=44402 AN62510 - Implementing State Machines with PSoC® 3, PSoC 4, and PSoC 5LP
Hi Odissey, Thank you for your comment. I appreciate your concern. In my defense, I can only say that this is an internship for me. I am not spending my college time on topics which are completely new to me. Since I am not an EE/CS major, I can only learn about such topics though internships, etc. Now will this stuff be useful to me in my future? I believe so. I plan to join graduate school in experimental physics and an overview of lab electronics is important along with optics and mechanics. I understand that one must be very good in a specific area. But also from my experience, while working on an idea everyone in the group pitches in. The more you know the better! It's a bit too late to change my major, and a bit too early to regret the lack of a permanent job for me lol
Well anyway I believe I am adding some questions (though mostly silly) to the CDC. The UDB datapath must be a really confusing topic for many people. So if anyone has an answer they may contribute. But after spending a whole day on Datapath Config, I found out that if I don't configure the datapath, my custom component gets mapped to PLD (which I should have known before).
@Bob: If the PLD component doesn't work for me, I'll try to configure datapath using carry-in again. But I found it quite hard.
@Dana: Thanks for your suggestion. I can test the verilog on an FPGA simulator.
No idea why my username is not visible in the above comment.
the forum sw has some flaws, so sometimes the poster's information get dropped.
Let me make a guess: Is your goal designing an electronic autocorrelator?
Pretty much! Expept the (quantum) source should be ideally random and any autocorrelation is due to (non-quantum) bias. Is there a simple way to check the autocorrelation of discrete data on chip?
No shortcuts. You'll have do the normal multiply & sum to get that. There will be some reductions since you are working on a binary stream. That will be a good job for the UDB- ALU