The UDB contains FIFOs and individual registers to support the datapath.
Does not look like they are general memory, eg. ability to wrap control around
them to implement dual port.
Consider trying a verilog definintion and see if it compiles ?
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I believe the best you can do is a 12x16 (12 addresses 16 bits wide) using parallel in/parallel out of the datapath.
Trying to store the other 4 words in PLD logic explodes to 1092 unique p-terms. There's only 384 unique p-terms on the part so that's not going to work.
Originally I was thinking you could double up on the PI/PO, but the issue is what happens if you need both 16 bit values from the same datapath at the same time.
You also have an IO problem. You're going to need to overlap the input and output lines, otherwise with control signals you're using 77 or 72 IOs.
And all of this is before routing considerations. So I'm going to say it isn't posible using a single PSoC5 LP as it is defined today.
Thanks Dana and Scott.
@Scott : what i am trying to do actually is emulate ata file registers. it's not actually 16x16, only one of them is 16bit. the rest is 8 bit. about the i/o lines, of course they're overlapping, because there are strobes(read/write control pins), or am i mistaking imagining them (the dual port ram)? i have no knowledge about the verilog, but willing to learn about it.
Okay, so a 15x8 and a 1x16? That should be possible in datapaths using parallel in/out and using the address as the datapath selector. Basically send PI in through and save to A0 (when write enable is set of course). On address match you simply load A0 through parallel out. (Consumes the status and control blocks). Use a lookup table on the high order bits to decode which datapaths to enable, and you're pretty good.
It is going to take some extra work to get there, but you're effectively turning the datapath into a byte memory cell with load and data lines. Make that your own component and it should be easy to build from there. And since the datapath area is memory mapped, your firmware will have direct access to that information as well.
Oh and by sharing I mean you'll have to use the pins in a bidirectional way outside of the PSoC. Use output enable to swap their direction based on write enable and you're golden. Otherwise, you won't have enough pins even with the largest PSoC 5 LP.
@Scott : Thanks for your insight. i will dig into this matter once i got my hands on psoc5 kit.
you may start right now! Download and install PSoC Creator 3.2 and begin reading the Component Author Guide and the Warp VeriLog Reference Guide. You may even start your design, since it will take some time until you will be familar with the new tools and start to upload projects into your PSoC5.
What is the dual port ram going to be used for and what performace specs
are you looking for ?
@Dana : as i said before, it was to emulate ata task file register. i want to make ata emulator with sdcard as data holder. as for performance spec, i would begin with PIO Mode 0 first, since i still have little knowledge about the ata protocol. it is 600 ns window between each strobe in mode 0. but in reality they were not so fixed. they can variate a bit faster. the strobe itself is around 100ns. initially i wanted to use interrupt, but since the 'other' fast mcu i had can not handle that, then it comes to my mind to use dual port ram for fast response.