I want to generate clock pulse whose frequency changes automatically from 100KHz to 400KHz with step of 100Hz per 1ms. i.e. at
You are asking for a .025% accuracy solution, so using internal clocks and their dividers or Wavedac8
component out of the question.
Several methods -
1) External DDS chip
2) External PLL
3) Verilog digital frequency generator solution, make calulations of
max clock f you need to see if this is feasable.
Cypress makes programmable clocks -
Thanks danaa, But I want to implement it using PSoC5 internal components available. I don't want to add extra component to add to the circuit. Actually I want to replicate an external clock device inside PSoC.
Verilog component might be a good idea, please share some reference.
The only applicable solution in the PSoC world I can see is to program a 32-bit wide UDB component performing that job.
This must be done in a HDL (Hardware Description Language) named "VeriLog" which already is installed together with the Creator-software. I admit: that is not an easy job, but it can be done.
The mentioned UDBs are running at up to 48MHz containing 2 FIFOs, some registers, programmable logic and an ALU that can be programmed to perform some simple arithmetic calculations.
A component built this way can made to run independent from CPU intervention after set-up.
If you examine the basic problem, your HF clock needs to be 400 Khz / .1Khz step =
4 Mhz. But that is compounded by the fact you want a linear relationship from 100 Khz
to 400 Khz, so that places further demand on starting clock F to divider chain, fractional
I woud presume.
You might investigate digital freq generators from the FPGA guys and see what verilog
you can get from them and the error calculations.
I googled "verilog frequency generator" and got quite a few hits.
Also try a google "digital rate multiplier verilog".
you can find PSoC5LP 24bit tunable frequency DDS component implementation in Verilog and demo project here. 24bit = ~0.01-0.1Hz precision in 100-400kHz.range. I don't see any problem updating frequency in SW interrupt with 1ms period.
If you want to do so without software code involvement at all, you can modify this component by removing ControlRegisters. Note that Verilog core gets data as parallell bus from registers, so for pure HW implementation you will need to feed those bus lines by hardware instead of ControlReg.
Thanks to all of you, Really you all have gave me a direction to think. I will revert back with some work and results, give me some time to juggle around.
Attached is demo project: DDS sweep frequency generator with hardware update. It produces digital output (50% duty cycle) of variable frequency in the range 100kHz -- 400kHz in 100Hz steps, 1 ms/step. You can change start frequency, frequency step, number of steps, update interval. For best accuracy use quartz stabilized clock. Without XTAL frequency noise is about 1E-3, with XTAL accuracy is about ~1E-6.
Project based on custom DDS24 component, written in Verilog for PSoC5LP (it will not fit PSoC4). DDS24 component library is included. To add component to this project in Creator go to Project->Dependencies->User dependencies and add DDS24.cyprj file.