Thanks. I am able to get LFCLK as an output to GPIO in Active mode.
But I am trying to assign 32 khz in deep sleep mode to one of the GPIO pins.
Looks like the pin is frozen -
GPIO output states cannot be changed during Deep-Sleep.
Thanks For the info.
I am able to get 8KHz clock in deep sleep mode using LCD drive in deep sleep mode.
Is it possible to get 32 KHz in deep sleep mode?
I have attached the project for reference.
DeepSleepILO.rar 1.8 MB
DSI connection is lost during Deep Sleep. That is why you do not see the clock when directly routed to a Pin during Deep Sleep. The max frequency using Segment LCD method is 8 KHz.
Finally I am able to get 32KHz WCO output in deep sleep mode.
We need to enable LFCLK as WCO in .cydwr. Now using the High Speed I/O Matrix (HSIOM), we can route this clock to Pin. In this project, we are routing to P1. Please note that this is only available for three Pins P1, P2 and P3.
The example project uses P1.
If you want to route it to P2, then configure P2 as an output pin in Creator and write:
*(uint32*)CYREG_HSIOM_PORT_SEL2 |= 0x0000F000 ;
Similarly, for P3, you need to write:
*(uint32*)CYREG_HSIOM_PORT_SEL3 |= 0xF0000000 ;
after configuring P3 in Creator as an output Pin.
I would be a great assist to all if you filed a case and asked Cypress
to update TRM, clocking section, and any applicable ap notes, like
the low power ap notes and the coming clock ap note. Just paste in
your findings when you file your CASE.
To create a technical or issue case at Cypress -
“Create a Case”
You have to be registered on Cypress web site first.