In Cypress help, documentation, warp verilog guide I see no operator listed -
But in Cadence manual this -
so I'm guessing thats a no for verilog then? the cadence manual is referring to VHDL, while the other is referring to verilog.
Seems like its hard to completely disassociate Warp VHDL and Warp Verilog, from the Cypress manual
Point being Verilog is RTL based like VHDL, and seems like its an extension
to VHDL at some level ? Not an expert here, you are talking to a dunce.
Thanks Dana, You've at least confirmed I wasn't just missing something obvious. If anyone else has any insight into this it would be appreciated. any kind of work arounds besides relying on the processor side of psoc? Thanks, scarlson