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I have interfaced ADC to PSOC 4 BLE and reading samples every 1 ms. So after WDT interrupt every 1 ms , adc wakeup and grab data and again go to deep sleep. I am trying to reduce the current consumption.
I have attached project in previous comment and check the current consumption image.
Please let me know for any changes.
I am using ADC at 1KHz sampling rate and operating in deep sleep mode.
i.e wake using WDT interrupt every 1 msec, grab the ADC sample and go to deep sleep.
In deep sleep, I measure about 1.1 uA and the duration is 1000 us. (Actual time measurement based on GPIO triggers.)
When the ADC is running (the instructions in the loop when not sleeping), I measure 800 uA for a duration of 35 us and other time its 1.3uA.
So the real average should be
35/1035 * 800 uA + 1000 / 1035 * 1.1 uA = ~ 20-50 uA.
Please check images in the attachment.
Why it’s taking more time to settle?
Current should be as low as possible.
Please let me know for any changes in the design.
One of the problems may be this (the reference) -
18.3.3 Low-Power Buffers
PSoC 4 has multiple low-power buffers divided into two
groups - fast and slow. These buffers take input from the trim
buffer circuit and drive the destination blocks. The fast buffer
has the capability to reach within 1 percent of the final value
in 9 us. The slow buffer can reach within 40 us. Multiple buffers ensure low reference-line capacitances, which in turn
reduces the settling time. Fast voltage buffers are used for
the references driven to the blocks that are crucial for system startup. These include the IMO, flash, low dropout
(LDO) regulator, low voltage detect (LVD), and brownout
detect (BOD) circuit.
The output of the fast buffer is driven to the slow buffer. This
ensures that the extra loading due to the non-startup related
blocks are isolated from those driven by fast buffers. Slow
buffers drive function blocks, such as SAR ADC and
Fast buffers are always enabled along with the bandgap
block; slow buffers can be individually enabled or disabled
by the user using the VREF_EN bits of the
PSOC 4 BLE Reference.jpg 50.5 K