What is the bit rate of the stream you are trying to generate ?
DMA and some code certainly can create a circular buffer by chaining.
Verilog a very good possibility.
Or use the Datapath and some ASM code.....
http://www.cypress.com/?rID=60720 DFB Assembler, MAC Topics
http://www.cypress.com/?app=forum&id=2492&rID=76907 DFB Assembler
https://www.youtube.com/watch?v=2UC4gCohrk8 DFB Video Part I
https://www.youtube.com/watch?v=6tr_CNWIA8M DFB Video Part II
https://www.youtube.com/watch?v=nIa4X7gES3k DFB Video Part III
Since the VeriLog resources are not able to access memory, an interrupt driven approach could do best.
A circular buffer can be implemented using pointer arithmetic and has a high performance when compiler's optimization is set.
Not a too difficult job.
Warp Verilog supports 32 bit registers, a clever combo of Verilog and DMA might
A SW approach begs the question, what is the data rate you are trying to achieve ?
The rate is 100 Kbps.
Thanks for suggestions!
Dana, you think I can do it by chaining DMA TDs? Any more clues about this? Any examples?
These discuss chaining -
http://www.cypress.com/?rID=37793 AN52705 Getting Started with DMA
http://www.cypress.com/?rID=82680 AN84810 PSoC® 3 and PSoC 5LP Advanced DMA Topics
http://www.cypress.com/?rID=44335 AN61102 PSoC® 3 and PSoC 5LP - ADC Data Buffering Using DMA
http://video.cypress.com/video-library/search/dma/ Videos on DMA
https://www.youtube.com/results?search_query=dma+psoc Videos on DMA (some overlap)
Hi, It should be possible with chaning DMA TDs. There does not exist example project exactly for this application. However, other examples as pointed out by Dana above should help.