The project you supplied misses the main loop. main() will start over and over again including PSoC component initialization.
Place at least a while(1); infinitive loop after your initialization.
To Bobs point you commented out your for(;;) so application falls out of main().
Note you use 2 Vrefs and 2 OpAmps to buffer the two Vrefs. You really only need to do
the left one and route its output to OpAmp2's NI input. Saving an OpAmp resource.
One additional consideration I am sure you are aware of is the exceptionally high Z levels
at the input amp, fdbk R values, etc.., very subject to noise pickup. So PCB layout very
http://www.cypress.com/?rID=39157&source=an61290 AN54181 - Getting Started with PSoC 3
http://www.cypress.com/?rID=39677 AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations
http://www.cypress.com/?rID=40247 AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations
http://www.cypress.com/?rID=39974 AN58304 - PSoC® 3 and PSoC 5LP – Pin Selection for Analog Designs
Great! Thanks! I thought is not possible...
As regular you are very helpful :)
You can't use that AD circuit as shown, its meant to operate on split supplies.
You can do a single supply version of it, eg. still bootstrap with + fdbk to raise
Z levels, but then bias circuit Z becomes the problem for practical values. Maybe
a real JFET current source would permit that.
As an aside the 10 uF block cap in that circuit can't be an ordinary electrolytic,
it has to have super low leakage to avoid latchup in the OpAmp.
To interface a piezo transducer I used a single supply circuit of charge amp.
Regarding the big Z in the circuit
"still bootstrap with + fdbk to raise Z levels, but then bias circuit Z becomes the problem for practical values" - what does it mean?
All piezo interfaces containt big Z impedance. Maybe it is reasonable to use external Opamp and not Psoc?
The judgment to use external OpAmp or IA should be made on
noise, bias currents, offsets, etc.. The primary issue here is the
biasing solution and its affects on loading of the Piezo.
You might consider doing some spice simulations to get a general idea
of how to proceed.
Note board prep for real hi z applications not trivial. Google "Bob Pease"
on ap notes for bias current and pcb design factors.