The SPI is done using cascadable 8 bit wide UDBs which must be programmed using VeriLog as HDL.The UDB already contains the needed FIFOs in input and output paths.
Not quite an easy job, but doable.
On the other hand: It could be managed to transmit 3 bytes via SPI to get 24 bits as a result.
Bob, thanks. I hadn't considered that SPI might send 3 8-bit bytes "contiguously". I'll give that a try and see how it works. In the meantime, someone at Cypress was able to locate (or create) an SPI component supposedly configurable for up to 32 bit length data items. I might try that as well...