1 Reply Latest reply on Aug 2, 2015 12:00 PM by Madhu Lakshmipathy

    Timing running FX3 GPIF2 @ 100MHz

    achim.hummel

      Hello,

         

      I'm currently designing a FPGA (Altera Cyclone V) core connected to the GPIF2 interface.

         

      Unfortunately I couldn't constraint my design that it is running at maximum frequency of 100MHz.

         

      Especially the CTL hold time of 0 ns is generating failing hold time violations.

         

       

         

      Could somebody successfully connection an Altera FPGA to the FX3 GPIF2 interface and

         

      running that interface @ 100MHz ?

         

       

         

      Any comment is welcome.

         

       

         

      Thanks,

         

      Achim