Jul 29, 2015
08:25 AM
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Jul 29, 2015
08:25 AM
I am using the Debug Printf UART functionality on a BLE Pioneer board.
This works properly if SYSCLK is set to 48Mhz. If its set to 24Mhz many of the displayed characters are garbage.
Has anyone else noticed this?
2 Replies
Jul 29, 2015
08:53 AM
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Jul 29, 2015
08:53 AM
Sounds like baud rate changed ? Would a clean and build recalculate
the divisors ? Not sure.
Can you see bit timing changed with a scope ?
Regards, Dana.
Jul 29, 2015
02:59 PM
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Jul 29, 2015
02:59 PM
I would suggest to check the clock accuracy in the clock view of the .cydwr-file. This may show different values for different system clock settings.
Bob