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I worked through the 42xx code here www.cypress.com/ for SPI TFT Color LCD240x320. The 4245 project compiled and ran on the Pioneer board as well as the 4200 Prototype board.
I duplicated the project and selected a CY*4125 AXI-483 for the uC and gutted the SD-Card and added in the SCB as a Motorola SPI controller. I assigned the pins and edited the TFT.C code to utilize the SCB component.
Everything compiled without error. I connected to the SPI TFT color display and nothing but backlight. Replacing the 4100 prototype with the 4200 prototype board and the display works. I have looked over the SCB property sheet which shows SCLK mode: CPHA =00, CPOL =00 and this matches the mode used in the original SPI Master control on the CY84245 ; however, I do not find a similar "MSB First" setting with the SCB.
I am missing something. I do not own a Saleae logic analyzer, but my dual channel scope seems to show MOSI and SCK and CS all performing. The D/C signal is a firmware controlled pin, and the Data/Command were only edited from SPIM_WriteTxData() to SPIM_SpiUartWriteTxData() based upon my interpretation of the datasheet for the component: SCB in SPI Master Mode.
In the grand-scheme of things this is not a big deal, but I have a number of the 4100 Prototype boards that I want to "consume" before using my 4200 boards and the current project in mind uses a SPI TFT color display.
Anyone see what I have done wrong? Thank you. 1st item on Holiday list is now a Saleae.
Regards,
Ray
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A quick answer might be had by printing project data sheets for both
4100 and 4200 and comparing .....
Also SPI in 4200 is 2x speed of the 4100.
Regards, Dana.
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I am having the same problem. I can run Ray Burnette's test program on a 4200M (CY8CKIT043) perfectly, but when I port the identical code to a PSOC5LP (CY8CKIT-059) with the same exact pins, I get nothing. I am using the same screen for both PSoCs. I suspect it's a SPI timing thing, but I can't figure it out. The SPI settings are identical for both PSoCs.
Any insights?
Best wishes- Jason
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There is probably a difference in SPI timing concerning the ss-line. I would suggest you (as a try) not to use the SPI's ss-line but create a pin (no hardware connection) that you pull low (pin_write(0)) before you start an SPI transaction and which you release (pin_write(1)) when the transmission is completely done.
Bob
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Didn't work. I pulled the SS pin off the SPIM and directly wrote to it. Still works on the PSOC4 but not the 5. Ugh. I think Cypress is going to need to support these types of displays at some point. It's trivial to get them working on Atmel or STM32.
//*************************************************************************************
void TFT_SendCMD(uint8_t cmd)
{ CS_Write(0); CyDelayUs(5); D_C_Write(0); CyDelayUs(4); SPIM_WriteTxData(cmd); CyDelayUs(10);CS_Write(1);}
//*************************************************************************************
void TFT_WriteData(uint8_t Data)
{ CS_Write(0); CyDelayUs(5); D_C_Write(1); CyDelayUs(4); SPIM_WriteTxData(Data);CyDelayUs(20);CS_Write(1);}
//*************************************************************************************
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Actually I moved the pins to another net and it started working. Pins 0.0-0.6 didn't work. But when I moved to 2.0-2.6 it's now working. Weird. I got no complaints from creator about the choice of pins.
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Does anyone know how to implement new fonts with this example?