I turned off optimization to see what results would occur, design blew up
on me, eg. would not fit resources. Unless someone else can see issue consider
posting a CASE -
To create a technical or issue case at Cypress -
“Create a Case”
You have to be registered on Cypress web site first.
Too bad, but Creator is right.
You defined in verilog
reg [1:0] byte_counter; // Keeps track of current color byte (Y or Cr or Cb).
and later you question
else if( byte_counter == 5 ) // Y(3)
color = DmaMSB[3:0];
Since this could never ever be, it was optimized out, leaving no reference to DmaMSB in the file which allows for optimizing out the whole register.