In AN65974, there is a section title General Formulas for Using Partial Flags. The wording seems clear and the examples that follow confirm what I'm reading. However, in the example FPGA designs, the logic seems to be missing 1 clock cycle in how it deals with the partial flags. I ran some RTL simulation on the project files and read the description in the application note.
According to the formula, if the watermark value is 6 for a 32-bit bus, the number of clock cycles for a write = 2. It says:
"The number of data words that may be written after the clock edge at which the partial flag is sampled low"
If FlagB is asserted low (after the rising edge #0), it is 'sampled' on the rising edge #1. Then, SLWR# can be asserted for two more clocks after that, meaning rising edge #2, and #3. It is removed after rising edge #3. Correct? Why does the FPGA example do this one clock earlier (also, for the read case)?
In the case of the attached project the FPGA Samples the Flag in the same clock cycle it went low.