1 Reply Latest reply on Sep 21, 2015 9:29 PM by madhul_36

    FX3 Slave FIFO Partial Packet

      I've read through AN65974 regarding the Synchronous Slave FIFO mode, and the associated FPGA example design.  It seems like the examples cover the GPIF cases where there is a full DMA buffer transfer, then a partial or zero-length transfer.  What about the case where the host is sending a partial packet to the FX3, like 128 bytes?  Is it possible to notify the FPGA there is data to be read from the FX3?  It seems like FlagC does not go high until the DMA buffer is completely full?  Is that correct?





        • 1. Re: FX3 Slave FIFO Partial Packet



          When a short packet is sent from the USB Side, the FX3's DMA Buffers get wrapped automatically by the internal libraries. So Flag C would get asserted even if you send 128 Bytes.


          Special Cases. Assume that your DMA Buffer size is 16K bytes. You send only 1024 Bytes (or exact mutiples of 1024 bytes < 16K) from a host. 1024 is a full packet in USB 3.0 and is not a short packet. So the buffer will not be wrapped in this case. So you need to send a ZLP (zero length packet) followin this 1024 bytes to get the buffer wrapped and flag C to assert low.


          If you send any other value other than multiples of 1024, then buffer will be automatically wrapped.




          - Madhu Sudhan