Have you configured the PWM trigger input as edge detect ?
Note All inputs are double synchronized in the TCPWM. The synchronizer is run at HFCLK speed. After that (except PSoC 4100 BLE, PSoC 4200 BLE, PSoC 4100M, and PSoC 4200M, (Timer/Counter, PWM modes)), these signals are synchronized with the component clock.
This would mean that you should lengthen your start-signal until the component clock goes high.
I thought his issue is triggering a UDB PWM, not a TCPWM......that TCPWM is triggering the PWM ?
Thanks for the replies,
Dana - yes you are correct in that I am trying to trigger a UDB PWM. I can't see any way to configure the UDB PWM block as anything other than edge triggered, the only trigger options are rising edge, falling edge or either edge (and I have tried all three)
Bob - Effectively that is what I have done with the PulseConverter block , I was wondering if there is any other way to do it that uses less resources.
Regards, Paul H
I would file a CASE on this. Since it is an edge triggered input you are dealing with something
here is really whacky.
You are correct.PWM can only be triggered on rise, fall, both edges.
To create a technical or issue case at Cypress -
“Create a Case”
You have to be registered on Cypress web site first.
You could use verilog or discrete logic, like create a simple 3 bit SR, re-circulating a
2 clock high pulse in it. Or try a LUT for a solution.
The pulse stretcher you are using only uses 3 macrocells.
Consider posting your project so forum can look at the whole picture, or extract
s simple subset of the problem and post that.
“Create Workspace Bundle”