Thanks for the prompt response.
I did think it was referring to triggers levels of cmos (70% Vdd), but just wanted to make sure it was not 1.8V core levels.
So no PLL, I guess is OK as I just want to keep same freq domain, could always switch over to IMO or ECO when I need higher speed.
Don't forget to put some series damping R, 10's of ohms, in series with
clock source to PSOC pin, layout dependent, to get good signal integrity.