This might help -
http://www.cypress.com/documentation/application-notes/an54460-psoc-3-and-psoc-5lp-interrupts AN54460 - PSoC® 3, PSoC 4, and PSoC 5LP Interrupts
http://www.cypress.com/documentation/application-notes/an72382-using-psoc-3-and-psoc-5lp-gpio-pins AN72382 - Using PSoC® 3 and PSoC 5LP GPIO Pins
This surely helped.
Could you please clarify the reason to having contiguous pins? I've attached a quote from AN45381 document.
Plus, I need two different interrupts for 2 digital input pins. Does the attached picture configuration allows me to get it or I have to separate the pins so each will have it's own port?
AN45381.JPG 53.1 K
Sorry, I meant AN72382 document
I think the contiguous issue is a limitation of the way the component was designed,
rather than a HW limitation.
If you want a different priority for interrupts you would have
to assign them to different ports, otherwise no reason to not place
them all in one port. Reading the status register in ISR and use of
masks will tell you what specific pins are generating interrupts.
Additionally you may connect an isr component to the signal of a pin which then will trigger an interrupt on the desired edge.