If the sample rate relatively low use an ISR that looks at each sample
and trigger code based on your breaker condition.
You could also use DMA to place sample in a control reg(s) and use compare logic
to issue a HW breaker.
The control registers are 8 bits. 16 bits is coming from the ADC. How do you merge the two together, pull data from the DMA and connect two control registers to a comparator block?
Maybe I miss something here, but: the values that the ADC delivers to the DMA are not software-corrected. So that means you will have the same offset there as you would have with a comparator.
Why don't you use a comparator, and provide its trigger level via a DAC? That way you can correct the offset it in software too...
And as a side-note: on the PSoC4 you could use the Sequencing SAR which has a limit-detection feature.
He is using PSOC 5LP, Seq SAR limited to 12 bits.
Here are some ap notes on A/D (and other) using DMA, AN61102 in particular.
http://www.cypress.com/documentation/application-notes/an52705-psoc-3-and-psoc-5lp-getting-started-dma AN52705 Getting Started with DMA
http://www.cypress.com/documentation/application-notes/an84810-psoc-3-and-psoc-5lp-advanced-dma-topics AN84810 PSoC® 3 and PSoC 5LP Advanced DMA Topics
http://www.cypress.com/documentation/application-notes/an61102-psoc-3-and-psoc-5lp-adc-data-buffering-using-dma AN61102 PSoC® 3 and PSoC 5LP - ADC Data Buffering Using DMA
http://video.cypress.com/video-library/search/dma/ Videos on DMA
https://www.youtube.com/results?search_query=dma+psoc Videos on DMA (some overlap)