thanks Dana.. It was informative, but still did not state what exactly to do with the pins physically.. to connect or not and to what was not made clear unfortunately..
The pins are left unconnected and the port is written with logic "0" for each
respective bit pin value.
Excellent question. It's my company's policy to never let a pin float. Each pin must have the following conditions. This is specially important when in sleep or idle mode:
- Input with pull-up (internal or external)
- Input with pull-down (internal or external)
- Output (set low or high as appropriate to the external circuit state needed)
Implementing one of the above precautions is to prevent a possible input oscillation due to a Radiated Immunity event (high electric or magnetic field disturbance) that causes the CPU to falsely activate a function or just create additional input path leakage.
I generally prefer an input with an internal pull-down.
(Sorry Dana. The knowledge-based article was of no help here).
The question to Cypress is: If I don't actively declare a pin as being used in my design, what is the default state of the pin? In this state, if I receive a AC superimposed signal from the external environment, what will happen? Excessive current draw? Internal IC interference with other internal circuits and components?
An alternate solution is to declare ALL pins with a condition listed above. The downside is if I add to the design and need another pin, I actively have to manage the pins rather than an auto-assignment.
Unused pins are High-Z which makes it easy to pull them up or down without using much current.
"The downside is if I add to the design and need another pin, I actively have to manage the pins rather than an auto-assignment."
This can be avoided when you do not lock the unused pins in the design. A new pin can then be taken by the fitter from the pool of unlocked pins.
An unrelated question I suppose, but is there ever a good reason to let the fitter assign a used pin to a random IO?
I would think needing to wire up hardware for use requires planning/knowing which pin is fit to where.
Thank you for the reply. I'm am fully aware of unlocked pins. However, the pins don't show up in the DWR pin list until they are placed somewhere on the TopDesign schematic. This means if I'd prefer to configure unused pins with internal pulldowns I need to declare ALL pins in the TopDesign with this configuration. If later I need to actually use one of the pins, I need to move a previous;y unused (but assigned pin) to the appropriate schematic page and connect it with the appropriate I/O definition.
A proposed change to the Creator is to have a System setting that allows the user to define unused pins as digital inputs with pulldowns (for example). The fitter would then make the desired assignments. If a pin later gets used, the user can drop the pin down in the TopDesign and assign as needed in the circuit.
I can assure users that unintended radiated RF fields can happen. A good example is the RF field generated by a cell phone. Although it would not appear to be a high field strength in watts, the Volts per meter can get very large if you place your design right up against a cell phone when it is transmitting. The volts aren't very high, but the "per meter" coefficient is very large when the distance is a few millimeters.
You are correct for those pins used in the design. Unused pins are assigned high-impedance analog without pullup or pulldown influence. The input can then act as a high-impedance antenna. If the field strength is high enough this can cause unexpected current draw internal to the IC. For example, if the high-I pin sees a 2V AC voltage and the pin is defined as a digital input, the logic input circuit will start conducting in the linear region possibly causing partial conduction of both high-side and low-side FET circuits. This may appear as a lower resistance short between VDD and GND. If your design is battery powered, this will eat away at your battery capacity.
Additionally, even if the unused input is not routed internally to other circuits, the additional current draw of VDD/GND mentioned above may cause VDD or GND "bounce" that may adversely affect other analog circuits such as ADCs or DACs.
The "best" approach is to proved a low-impedance path to either VDD or GND. It will help to stub externally-induced RF energy through the resistance as well as make it less likely for the pin to act as an antenna, The pullup/pulldown resistance available on the PSoC should be sufficient in most cases.
There is a debate in the RF Immunity mitigation circles as to which is better: Internal RF stubs or external?
The external stub camp believes that any stubbing currents minimize the VDD/GND bounce issue inside the IC I mentioned above.
The internal stub camp believes that an external stub requires external resistors which require traces. These traces can act as antennas making it more likely to absorb RF energy. Wheres internal stubs with NO traces on unused pins are much less likely to absorb RF (at least below TeraHertz frequencies).
As an extreme example of the external stub camp: A colleague was using a >120 pin SPANSION device. However he only needed 12 I/O and VDD and GND. The remaining unused I/Os were connected to GND using 100K resistors. This meant that he had to find locations for 88 resistors and route traces to them. Ideally, the shorter the trace the better (shorter trace - higher frequency susceptibility). With 88 resistors to route, a short trace is not always an option.
Sorry for my longwindedness. I feel particularly gabby today. Either way, I hope this helps someone.
Whatever comes first, PCB or software?
At the stage of proof-of-concept there is no pcb yet. So letting the fitter assign the pins will find a working solution. This might fail when the pins are assigned manually.
No, the longwindedness is very useful for learning
That is interesting that the RF is causing enough induction on the pins to affect the power rails. I made a small battery-powered device, and it seemed to perform perfectly once we got it setup, but we didn't try it with alot of RF activity on top of it. I'm curious if I can reproduce the same issue on that board with some testing...
At some point, if you need highly sensitive electronics to work in RF environments, I would think you would use some shielding of some sort to prevent the RF from reaching the circuits (We are using the CYBLE-022001-00 module which has some shielding planes on the PCB and module to mitigate this).
Trying to wire alot of pull-down resistors like that sounds brutal; (And I think you meant shorter trace = less area for frequency susceptibility )
If your circuit is an intentional RF receiver, you'd be better off with a matching impedance to a desired higher-Q bandwidth. I was more concerned with circuits that are not intended to receive RF. A good low-impedance source to GND or VDD will virtually eliminate unintended operations. Besides, although shielding might be effective, it is more costly than external or internal pullups/pulldowns.
Shorter trace = shorter wavelength = higher frequency before RI susceptibilities. The trace area is mostly inconsequential. The shorter trace is more consequential.
I suggest, do not leave unused CMOS-pins as high-z inputs. If the pin does not have any connection to the outside world, define it as push-pull output and switch to HIGH or (preferable) LOW.
Yeah, intentional matching will yield better Q. But, in my case we are using the module with built-in antenna.
True, shielding versus pull-resistors is a trade-off between cost and quality. It all depends on what you need for the application-in-use
And, depending on what frequencies of RF you need to avoid or are worried about, shorter/longer traces will be more effective I agree.