2 Replies Latest reply on Oct 8, 2015 8:25 AM by shkuc_292731

    Problem with SlaveFIFO ShortPacket/ZLP




      I am checking the Slave FIFO interface on FX3 superspeed explorer kit connected to Xilinx SP601 FPGA Board.


      I have successfully done the evaluation on the StreamIN & Loopback modes. I am facing some issues on the ShortPacket & ZLP modes.


      As per the application note - AN65974 , i have changed the SW8 on the FPGA board & loaded the binary named as "SF_shrt_ZLP.img" which came with the application note. After that i have Opened the control Center -> selected the Bulk IN Endpoint -> Clicked 'Transfer Data-IN '


      I am getting the following error "BULK IN transfer failed with Error Code:997"


      Am i missing something ? Any immediate help will be greatly appreciated.




      Thank you,





        • 1. Re: Problem with SlaveFIFO ShortPacket/ZLP



          Did you make sure that the LOOPPACK_SHRT_ZLP macro is disabled and STREAM_IN_OUT macro is enabled in the firmware?




          -Madhu Sudhan

          • 2. Re: Problem with SlaveFIFO ShortPacket/ZLP

            Hi Madhu Sudhan,


            Finally a reply is given for my post. Thank you. I appreciate it.  :)


            I just experimented all the things & solved most of the issues pretty much by myself. But still some issues are there.


            So here i will post my findings so that it will be helpful for some other developers like me.


            The FPGA bianry provided with the AN84868 application note is not working. Since i was testing the FPGA with this binary, i have wasted a lot of time. This binary seems to be working only with Loopback mode. Its not working for StreamIN, StreamOUT, ZLP & ShortPacket modes. I have used SlaveSerial interface to program the FPGA.


            Path : AN84868-Configuring an FPGA Over USB Using Cypress FX3.zip\AN84868 - Source files for FX3 Firmware\AN84868_Project_files\fpga_write\fpga_write\fpga_master.bin


            I couldn't find any information about connecting the SuperSpeed explorer kit SPI lines to FPGA board in the application note.
            Instead i found a diagram of FX3DVK board connected to FPGA board. 


            A sample image like this would be helpful, so please add this in the document.



            The .bit file provided with the AN65974 application note is working with out any issues on all the modes. Now i am programming the FPGA via JTAG.


            Path : AN65974_Source Files\FPGA Source files\fx3_slaveFIFO2b_xilinx\fpga_slavefifo2b_verilog\slavefifo2b_fpga_top.bit


            So i have checked all the five modes in 32bit GPIF bus width. If i use the 16bit GPIF means i am getting some issues.


            On the firmware side is , i have Changed the macro "CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT"as '0' & changed the GPIF socket configure API as "CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET_0,3,CyFalse,0);". But i am getting buffer over run error on the StreamIN mode. The ZLP & Short packet modes are working as expected.


            Do you have any idea why this is happening ?