MrinalMani, From your previous posts, you want keep updating PWM at 10us intervals. The problem is that ISR latency is about 15-30us, so using this (software) approach you might miss half or more update cycles at least. As Bob Marlowe pointed out, 10bit * 100kHz = 100MHz, but the fastest PSoC CPU frequency is only 80MHz, so you have to relax specs in half first. Then look into PSoC hardware solution avoiding CPU if possible (use schematic, Verilog, Datapath and DMA).
Thanks for the reply.
Yes, I realize that my specifications lead to 100MHz speed.
So instead of 10 bit (1024 steps), 7.6 bits (200) steps will do. This leads to maximum operating speed of 20MHz. (200 steps per 10us).
But 30us latensy is way way too much!
Isn't the interrupt supposed to be serviced within 8 to 10 cycles?
I had read somewhere that with NVIC implementation, the maximum delay is nearly 8 cycles. (Don't remember the exact number, but it's close to 8 or 10)
30us delay is nearly 1000 machine cycles at 24 MHz HFCLK. Why does the processor need 1000 cycles to service an interrupt!!?
Maybe there is a way to speed up isr execution, to check actual latency I suggest to toggle a pin on interrupt and observe it on a scope. If I may ask, do you want to make a feedback loop to control power output, or you want to modulate PWM with sine, or you want to implement a voltage ramp with some fixed parameters?
I want to modulate PWM with sine at a carrier frequency of 100KHz
There are many ways to make sine modulation. Attached is one idea using digital sine wave generator based on a lookup table. I didn't test the project, but it compiles OK in Creator 3.2 / PSoC5LP. Note that it will not fit PSoC4.