I'm trying to resolve a timing violation reported by Creator 3.2 SP1 (220.127.116.1175) with the CY8C5868AXI-LP035. Please refer to the attached schematic page.
I'm driving all of the counters an the SRFF from the same SampleClk (32MHz, derived from the 64MHz PLL output). I'm getting a timing violation from the "TC" output of B3Counter to the Q output of the SRFF. The violation is an async path. The source clock is "CySampleClk(fixed-function)" and the destination clock is "CySampleClk".
Aren't these the same clock? Is there something goofy going on internally when using a fixed-function timer implementation? If I remove the SRFF and connect the "TC" output directly to the MUX selector input I get no timing violation which is also confusing. I am using a fixed-function timer implementation as I'm out of UDBs.
Also please ignore the implementation bug where I'm using B2Counter's TC pulse output to drive the enable signal of B3Counter. The issue at hand is the async path that I can't rationalize nor figure out how to correct.
Answering my own question here... a synchronizer is required when connecting the output of a fixed-function block to anything back in the UDB. See page 20 of AN81623 under "Topic #7: Interface with Fixed Blocks.
TL;DR: the static timing analysis currently cannot "see" into the fixed blocks connectivity so they're flagged.