I have been trying yo set LFCLK to Timer in my PSOC 4 BLE, and i could not do this..., it is a problem, because in DEEPSLEEP HFCLK is shutdown, so i cant put my IC into DEEPSLEEP during long period....
I hope that someone can give to us one answer
Take a look at this thread, try the idea suggested for routing LFCLK to
a pin, then instantiate an external clock ....
Also pay attention to sleep tables (2) posted as well in thread.
Even your timer will not run in DeepSleep mode, only WDT will be active and running on LFCLK.
Here is a representative solution, see attached.
Note in deep sleep UDB counter will not run.
PSOC 4 LFCLK to UDB_0.jpg 46.3 K
Thanks all for the responses,
The schematic of the external pin routing is not quite what I meant, the LFCLK should be routed to the clock of the counter, not the count input. Regardless I can see now that the UDB blocks are only retained, not operational, in deep sleep, so will likely have to implement in firmware via interrupts anyway.
The clock input of a UDB counter is a synch clock for the count input.
From the datasheet -
Clock The functional behavior of the clock input differs for the fixed-function Counter compared
to the UDB Counter.
For a fixed-function Counter, there is no count input. A fixed-function Counter
updates (decrements its internal counter) on every rising edge of the clock input.
For a UDB Counter, both the clock and count input appear on the Counter symbol.
The clock is used to sample the inputs of the Counter component. The UDB Counter
is implemented as a synchronous counter that uses the clock input only as a
synchronization clock. All inputs of the Counter must be synchronized to the clock
input to avoid setup violations. This also makes sure that the edge-detect circuitry in
the UDB Counter implementation functions properly.
Count In a fixed-function Counter, there is no count input on the Counter symbol. A FF Counter
updates its internal count on every rising edge of the clock input.
For a UDB Counter, the Counter updates its internal counter with an edge-detect logic to
determine an update event. The source signal for the update event depends on the clock
mode of the UDB Counter. The edge-detect logic is clocked using the clock input. Both
edges of the count input must meet setup to the clock input; therefore, the maximum
count input is one-half of the clock input frequency.
For a UDB Counter in the Up Counter or Down Counter clock mode, the edge
detect logic detects the rising edge of the count input synchronous to the clock input.
Depending on whether the Counter is configured as an up counter or down counter,
the edge detect event on the count input increments or decrements the Counter,
respectively. See Figure 5 on page 25 for a functional description of the Up/Down
For a UDB Counter in the Count Input and Direction clock mode, the edge-detect
logic detects the rising edge of the count input synchronous to the clock input.
Depending on the whether the "upndown" signal is a 1 or a 0, the edge-detect event
on the count input increments or decrements the Counter, respectively. See Figure 7
on page 26 for a functional description of the Counter in Count Input and Direction
For a UDB Counter in the Clock with UpCnt & DwnCnt clock mode, there is no
count input. The Counter update event is determined by a combination of the edge
detect logic on UpCnt and DwnCnt signals synchronous to the clock input. See
Figure 9 on page 28 for a functional description of the Counter in Clock with UpCnt
& DwnCnt clock mode.
This is late but we are trying to implement the same thing. One possible solution is to use the WDT timers ( from the clocks tab in the cydwr page ) and set the mode to 'Periodic Timer'. How did you implement it ?