are you looking to measure DC or AC signal?
I am looking to measure DC signal.
Depending on how you use PGA you may have to bias it up so
thats its output falls into its CM range.
If you are handling very small signals then you have to be fully aware
of offset, noise considerations. Here is one approach to the problem -
http://www.cypress.com/?rID=49159 AN66444 - PSoC® 3 and PSoC 5LP Correlated Double Sampling to Reduce Offset, Drift, and Low Frequency Noise
Ok, I am going to take a look at these techniques that you said. Thank you Dana!
Daniel It is likely that you having issue with PGA offset voltage. Imagine that PGA2 has offset +1.5mV, and you feeding its input with +1mV from PGA1. In such case PGA2 output will become <0. Try to change one or both PGA's to inverted PGA. As always, measuring small voltages, it is advisable to use differential measurement approach and modulation to get rid of the drift. Another option is to use DelSigADC set to 24 bit and max buffer gain (+8), differential. This will bring you to sub-mV region.
One other solution is to use a high performance IA external to PSOC. They
are laser trimmed at factory, have very high G, excellent CMRR. Analog
devices leader in that area.
I thought that the offset could be the reason of the voltage discrepancy, but I am not sure how to measure it in psoc 5LP. I tried to use inverted PGA but with this I got another problem. The inverted PGA does not accept internal Vref, and when I try to use external Vref = Ground ( the external ground pin of psoc) the results are totally strange ( even if I use just 1 single inverted PGA ). But when I use just 1 PGA with Vref = internal Vss everything works fine. As you said, I will start to considerate using other approaches like using the differential measurement or DelSigADC or using the techniques said by Dana. If I got any new advancements I will post. Thanks for the hints!
I am avoiding to use external components of PSoC, because I want to develop a compact circuit. And since I am new on psoc development I want to learn what I am doing wrong.
Daniel, where this uV-level signal comes from (what kind of sensor)? What is estimated output impedance and range? Try to utilize DelSig ADC in differential input mode, buffer gain x8, internal reference set to +-0.125V, resolution 24bit. Then 1-bit would correspond to 2x0.125V /8 /2^24 = 2E-9V = 2 nV. Realistically, due to noise issues, is to get effective resolution about 20 bit (~30 nV), which is still very good. Notice, that DelSigADC has a modulation input, which you can utilize to invert the incoming signal back and forth, and subtract the inevitable offset voltage. I further recommend this article from Electronic Design (Offset Compensation Technique Improves Bridge-Configured Sensor Performance): http://m.electronicdesign.com/analog/offset-compensation-technique-improves-bridge-configured-sensor-performance and this one: http://m.electronicdesign.com/components/use-strain-gauge-based-sensors-pro
At first the signal is coming from the Vdd of the PSoC, and I divide the voltage among some resistors of 10Kohms and 330Kohms to reduce it. The resulting voltage is something near 16mV, but as this is going to be a prototype I intend to get smaller signals after getting this worked. I will try to use the DelSig ADC and the Offset Compensation Technique that you said. Thanks for the hints!
There is a fairly simple method to proceed to establish how much G
1) Start with desired output, max you want. For sake of argument pick 1 V.
2) Choose resolution you want at full scale. Again as example pick 1 mV.
3) Then rough A/D size is ~10 bits.
4) Do you have high CM environment, like a bridge. If so then solution
should have a differential amp at beginning of signal chain. If not single
ended is fine.
5) Let Vmaxsensor =~ 1 mV.
6) Now Gtot = 1 V max out / Vmaxsensor ~= 1000.
7) 1 LSB on A/D, input referred, is now 1 uV. If that’s not low enough increase
the # bits of A/D, or use averaging in SW to increase effective ENOB of A/D.
8) Take as much G as you can at sensor end of signal chain, for noise and
S/N considerations. The remaining G you take in the rest of the signal path, in
this case the A/D buffer G. Note if you take G via A/D buffer, its side consequence
is the A/D input CM range is no longer R-R. Its roughly 100 mV off the rails.
So that reduces total CM range in the design. Also keep in mind because it is a
buffer if you use it you do not have to be concerned about prior stage loading.
9) Do a noise analysis to determine what the effective S/N is going to be in
10) When working with low level signals you have to be very concerned with
drift, offsets, layout, especially if seeking absolute accuracy. So do an end to end
analysis of errors, offset, drift, temp, PSRR, CMR……to do the job right. The way
to do that is extensive use of superposition and normalize all errors to a common
reference, like PPM, or V, or %, or LSBs (which is ultimately what you want).......
and add them up.
This is a bit oversimplified but you get the idea.
Some useful ref material –
After some tests I can confirm that the output voltage discrepancy become from the DC offset. I guess It just needs to be configured, but I don't know how to clear up the offset in PSoC creator, considering that the PGA is built on-chip. In off-chip PGA I could just use a potentiometer in the offset pins and all could be resolved. Any ideas ?
You can use the article that odissey1 posted earlier (quite simple and effective),
or use CDS link I posted.
Or use mux, switch a known V into A/D, measure the offset, and use an IDAC
to inject a current into PGA input to null the offset out.
Or use a mux, a bare PSOC OpAmp, mux your own G R's, and traditional offset potentiometer
at the summing junction.