i am trying to implement a sync fifo 2 bit that has two output eindpoints and two In endpoints, i create the these enpoints in the descriptor and also create a DMA channel for each endpoint , but i still cant get working .
how can i implement a slave fifo with 2 out endpoints and 2 in endpoints
Can you please explain where exactly it goes wrong? I would recommend you to create a Tech Support Case for further analysis of your issue.
- Madhu Sudhan