It is due to the limitation with the GPIF II Designer. We recommend you to add a wait state (which waits for clock cycle) between TH1_RD and TH0_RD_LD states.
Have transition from TH1_RD to wait state with equation as "DATA_CNT_HIT" and have transition from WAIT to TH0_RD_LD state with equation as "LOGIC_ONE".
Thank you for your answer! I can not wait one more circle. Could I circumvent this limitation in this way?
I've found a very simple model for continuous input and I've changed it to output.
Please see attached project. I've built C header output two times: one for Thread0 and one for Thread1.
Then I've found only one bit difference in state machine array outputs. This model has only 3 states and
it is simple to try to change bits in C header manually. Will this bad way be successful?
ltc2203.cydsn_.zip 5.7 K