Thanks for your help.
What about internal reg cnt? I also cant initialize it. :(
So, the only solution is to add a reset button to initialize all the outputs and internal regs and to do so i have to bring MCU in loop as well to generate reset pulse after some delay?
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Isn't that your reset condition?
always @(posedge clk or negedge rst) begin
Yeah, it is but still i have to generate negedge from MCU after some delay to reset my component at start. Before I was thinking of making my component without reset button and initialize everything at the start while declaring them as regs. But later I came to know that it isnt possible in PSoC's verilog and you confirmed it as well while debugging my code.