7 Replies Latest reply on Oct 25, 2015 7:43 AM by user_275099341

    raw pld

    user_275099341
              Hi everybody. say, I want to use a single PLD "as is": connect signals to it's 12 inputs, and route out it's 4 outputs. and I want to read and write this PLD's registers. how can I do this? I understand, that I need to create component, which will synthese in a single PLD. that will give me a location of this PLD... but I want also to connect in and out signals, keeping bit order, if possible.   
        • 1. Re: raw pld
          user_1377889

          All you want can be done with VeriLog. In your Creator installation you find

             

          A Component Author Guide

             

          and Warp Verilog Reference Guide

             

          In Verilog you just describe your in- and outputs and define the equations.

             

           

             

          Bob

          • 2. Re: raw pld
            user_342122993
                    ender11, AFAIK the only (official) access to PLL is through Verilog, which will heavily optimize placement, there no guarantee it will eventually reside in a single PLL. Once compiled (sinthesized), there no ways to change/reprogram Verilog component operational behavior at run-time.   
            • 3. Re: raw pld
              user_275099341
                      no, that will not work. I thinking about initializing UDB via registers in software, but connecting signals will be rather difficult task... or, may be, if you are serious about verilog implementation, you can tell me how to instantinate a single PLD and assign signals to it?   
              • 4. Re: raw pld
                user_1377889

                Why are you fixed to a single PLD? There are some within the PSoC, two within an UDB. You can write to the inputs using register access or with signals. As Odissey stated, noe of the UDBs, PLDs or SCBs are (easily) re-programmable at run-time, but of course are re-programmable at design-time.

                   

                If you are a bit more specific or if you can give us an example we could be of more help for you. Read in the manuals I suggested.

                   

                 

                   

                Bob

                • 5. Re: raw pld
                  user_275099341
                          why not "ajust" components in runtime? "psoc3 registers TRM" states that you can write to PLD's CFG registers, altering product terms config bits and or terms config bits. so, we can switch PLD in desired configuration, but fitter connects signals in twisted order.. the idea was to use PSOC feature of RAM configurable PLD and step beyond the abilities of the conventional CPLD. more in focus: emulating keypad matrix. "rows" inputs are fed into PLD inputs, PLD outputs gives you "columns" with "keys pressed". software only modifies PLD configuration, minimizing input-to-output delay.   
                  • 6. Re: raw pld
                    user_1377889

                    OK, ender11. Try it.

                       

                     

                       

                    Bob

                    • 7. Re: raw pld
                      user_275099341
                              it will be no wonder if cypress has undocumented names for PLDs, like those for DPs...