1 Reply Latest reply on Nov 3, 2015 11:53 AM by userc_40401

    Query regarding Creator 3.1 vs later version datapath configuration for UDB components



      I have experienced problems since updating from Creator 3.1 with a PSoC 5 design implementing a custom SPI bus to run at high speeds for interfacing an SD card. It uses a component built in the UDB editor (as my verilog skills are non existent). I previously posted a query at




      I was advised to open a MyCase, but never got around to it due to other things getting in the way. Now my job requires me to return to developing my system, I have investigated the problem again to get back up to speed with my source code. Before getting back to posting a MyCase, I thought I would query the community - there is only one difference between generated verilog between Creator 3.1 and later versions:


      Creator 3.1:


          8'hFF, 8'h00, /* CFG9 */
          8'hFF, 8'hFF, /* CFG11-10 */


      Creator 3.3:


          8'hFF, 8'h00, /* CFG9 */
          8'hFF, 8'hFF, /* CFG11-10 */


      Can't tell if the above will post in a legible fashion.. However Creator 3.1 uses SC_FIFO1_ALU in the datapath configuration section, whereas Creator 3.3 uses SC_FIFO1__A0 in the corresponding location.


      I have found that I can override the verilog generated by Creator 3.3 by creating a verilog file as a component item in the UDB component in my project and pasting in the Creator 3.1 version of the verilog. This avoids the problem (so long as I don't need to edit the component design), but leaves me wondering if I'm relying on a bug in Creator 3.1 and should change my design, or if there is a bug in later versions of Creator.