I'm trying to interface a CY7C1370D SRAM with a Spartan 6. I managed to have something working but I think is not properly done because sometimes the data read is corrupted.
FPGA clocks the SDRAM through an ODDR2.
Data goes to IOBUF. I would like to synchronize data with clock in order to have a precise relation between the two, especially in the read path.
Has anybody already done something similar?
The best place to look at this will be in the FPGA forums. Cypress does not have a standard interface with a Spartan FPGA. Since in an Pipeline the data is available after the next clock cycle please check in the FPGA logic if this is taken care of. If you need any help from us about understanding the SRAM interface, let us know about it.