3 Replies Latest reply on Nov 17, 2015 7:48 AM by RaAl_264636

    SRAM size


      Hi all,




      I'm new to this part of things so bare with me. 




      I'm setting up a project, where I will need to monitor at least 3 ADC streams, all coming in via SPI, where I will be doing FFT's on them.  Now the size array I need to be doing FFTs on will be 40kBytes, so I can see a 1Hz wave (I'm sampling at 10Khz and have 32 bit depth).




      Now this means I will have 120kByes of data at a minimum.  way more than the PSoC 5LP has available in SRAM.




      What I'm wondering is how should I go about planning to do this?  I have never used external ram before but it sounds like this might be my best option.  if so, is there a way that I would do the FFT on the data while its actually on the RAM without moving it back onto the SRAM?  or would I move it back onto the SRAM before doing the computations?




      I figure a possibility would be extending my memory location addresses, but I have no idea how to even conceptually think of that.  




      Any help would be great, this is a new concept to me and I HAVE to figure it out very soon or I will be forced to switch to a chip other than PSoC.. which I really do not want to do since I love PSoC.







        • 1. Re: SRAM size

          Have a look at the External Memory Interface (EMIF) component for PSoC3 and 5. When that is usable for you... Needs a lot of pins.





          • 2. Re: SRAM size

            Hi Bob, 




            Thanks for the quick reply.  If you don't mind I have another question.  


            What kind of ram should I use or could you point me in the right direction to figure that out for myself?  I would like it to act as normal to the sram as possible, it states the EMIF supports synchronous SRAM, asynchronous SRAM, cellular RAM/PSRAM, and NOR flash.




            I'm guessing I probably should be looking at either synchronous SRAM or asynchronous SRAM, and coming from basic theory I know synchronous is generally a better way to go, but I know asynchronous is easier.  My main concern is the ability to properly perform the in place FFTs on the external SRAM.  




            any input on this would be appreciated







            • 3. Re: SRAM size

              Hi scarlson,




              the decision should be made upon speed needed and if the data has to be stored even when the device is powered down.




              If it has to be stored, you should use either a battery-backup solution for the (S)SRAM or a cellular / PSRAM.


              If it doesn't have to be stored, you can either use a synchronous or asynchronous SRAM. If you need (really) fast speeds, you'll have to use synchronous SRAM - however, then you also might need a special PCB layout.


              So, I think the first thing to be done is to place some 'pseudo' ADC values in code space to check how long the device needs for one calculation cycle for a single channel.


              After that, you can decide if a asynchronous SRAM will be enough (I assume synchronous RAM is more expensive).