As you know, Creator supported by Warp-Verilog
I don't know Verilog-AMS is support the Creator
Thanks for the reply.
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Under Programs -> Cypress -> PSoC Creator 3.0 -> Component Development Kit you will find the "Wartp VeriLog Reference Guide" which will show you what is included. Mostly the difference to Verilog is that there are *NO* simulation statements supported.
I asked about Verilog AMS because the AMS supports the analog part.
I'll try another way.
I think this is an interesting theme
Because, PSoC schematic is finally written in Warp-verilog,
Besides, PSoC has analog circuit of couse.
So, It can say the Warp-verilog is kind of AMS-Verilog(Analog-Mixed-Signal)?
I'm not shavvy so much
No, Creator does not support Verilog AMS. Also, calling it Warp-Verilog is misleading. It supports a subset of synthesizable IEEE Verilog 2001/2005-- industry standard for synthesis tools. In simulation, you can file-io for instance and in synthesis, there is not good way to translate that into hardware. All synthesis tools only support a subset of HDL (Verilog or VHDL)
Back to Verilog AMS, Creator only supports connectivity for analog modules. This means it supports a wire of type "electrical" and currently it can only be used for connecting analog terminals. In a sense, this is a mini subset of Verilog AMS but hardly can be called as Verilog AMS. Also, the design rule checks for analog wires are different from digital wires in Creator.
Having said that, all Creator schematics get translated to Verilog and this Verilog IS Verilog-AMS compatible. Problem is that you may not have lower level models for the primitives. You can find/see this Verilog netlist in the output directory :-)
Hope that helps.
@hdm I think you are not quite right. Warp Verilog allows analog and digital description of signals and functions.
Yes, it allows and understands digital functions.
Not analog functions. Just connectivity and instantiation of analog primitives -- which are kind of like black boxes. It does not understand what is in that black box.
For instance: Warp will not understand the following Verilog-AMS function (a diode example from wikipedia)
inout a, c; electrical a, c; parameter real IS = 1.0e-14; // User-configurable saturation current real idio;analog begin idio = IS * (limexp(V(a,c)/$vt) - 1);I(a,c) <+ idio;end
Analog connectivity: Fine. Funcationality and any kind of auto synthesis: No
One doubt...How can I instantiate the analog primitives?