10 Replies Latest reply on Jul 23, 2014 8:42 AM by alexandre.amaral

    Verilog AMS

    alexandre.amaral

      PSoC Creator supports Verilog AMS?

        • 1. Re: Verilog AMS
          junichi.hiraoka
                  As you know, Creator supported by Warp-Verilog   
          I don't know Verilog-AMS is support the Creator   
          Maybe not   
          • 2. Re: Verilog AMS
            alexandre.amaral

            Thanks for the reply.

            • 3. Re: Verilog AMS
              user_1377889

              Under Programs -> Cypress -> PSoC Creator 3.0 ->  Component Development Kit you will find the "Wartp VeriLog Reference Guide" which will show you what is included. Mostly the difference to Verilog is that there are *NO* simulation statements supported.

                 

               

                 

              Bob

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              • 4. Re: Verilog AMS
                alexandre.amaral

                I asked about Verilog AMS because the AMS supports the analog part.

                   

                I'll try another way.

                   

                Thanks.

                • 5. Re: Verilog AMS
                  junichi.hiraoka
                          I think this is an interesting theme   
                  Because, PSoC schematic is finally written in Warp-verilog,   
                  Besides, PSoC has analog circuit of couse.   
                  So, It can say the Warp-verilog is kind of AMS-Verilog(Analog-Mixed-Signal)?   
                  I'm not shavvy so much   
                  • 6. Re: Verilog AMS
                    haneef.why

                    No, Creator does not support Verilog AMS. Also, calling it Warp-Verilog is misleading. It supports a subset of synthesizable IEEE Verilog  2001/2005-- industry standard for synthesis tools. In simulation, you can file-io for instance and in synthesis, there is not good way to translate that into hardware. All synthesis tools only support a subset of HDL (Verilog or VHDL)

                       

                    Back to Verilog AMS, Creator only supports connectivity for analog modules. This means it supports a wire of type "electrical" and currently it can only be used for connecting analog terminals. In a sense, this is a mini subset of Verilog AMS but hardly can be called as Verilog AMS. Also, the design rule checks for analog wires are different from digital wires in Creator.

                       

                    Having said that, all Creator schematics get translated to Verilog and this Verilog IS Verilog-AMS compatible. Problem is that you may not have lower level models for the primitives. You can find/see this Verilog netlist in the output directory :-)

                       

                    Hope that helps.

                    • 7. Re: Verilog AMS
                      user_1377889
                              @hdm I think you are not quite right. Warp Verilog allows analog and digital description of signals and functions.   
                         
                      Bob   
                      • 8. Re: Verilog AMS
                        user_1377889

                        Here is a link to some documentation regarding Warp Verilog www.cypress.com/ 

                           

                         

                           

                        Bob

                        • 9. Re: Verilog AMS
                          haneef.why

                          Yes, it allows and understands digital functions.

                             

                          Not analog functions. Just connectivity and instantiation of analog primitives -- which are kind of like black boxes. It does not understand what is in that black box.

                             

                          For instance: Warp will not understand the following Verilog-AMS function (a diode example from wikipedia)

                             
                              inout a, c;      electrical a, c;      parameter real IS = 1.0e-14;  // User-configurable saturation current    real idio;
                          analog begin idio = IS * (limexp(V(a,c)/$vt) - 1);I(a,c) <+ idio;end
                             

                             
                          Analog connectivity: Fine. Funcationality and any kind of auto synthesis: No
                          • 10. Re: Verilog AMS
                            alexandre.amaral

                            One doubt...How can I instantiate the analog primitives?