3 Replies Latest reply on Nov 18, 2015 8:22 AM by prji.glitch_1505996

    R_USB2 and 3 connection

    ronald.jansen_1523006

      Hello,

         

       

         

      Is it possible to have the R_USB2 and 3 share a via with a power decoupling capacitor? Or will the ground noise cause unacceptible levels of noise on the USB bias?

         

       

         

      Thanks in advance.

         

       

         

      Best regards,

         

      Ronald Jansen

        • 1. Re: R_USB2 and 3 connection
          prji.glitch_1505996

          Dear Donald,

             

               It depends on the power pin to which ur decap is connected to and your GND plane routing. 

             

          Tnx

          • 2. Re: R_USB2 and 3 connection
            ronald.jansen_1523006

            It would probably be one of the core power supply decoupling caps. The ground plane is uncut, except for the vias running through. Actually there is 2 ground planes. One on each side of the board, below the component planes.

               

            What would be the preferred location for the crystal? If I would put it next to the chip, it would be in an area where all the decoupling for the USB power supplies is. If I would put it at the bottom side, it would require via's, in expense of the breakout of the digital signals. It seems there is no real pretty solution. I am used to crystal pins being at the edges of the chip, but unfortunately here this is not the case.

            • 3. Re: R_USB2 and 3 connection
              prji.glitch_1505996

              Hi Ronald,

                 

                               It is not advisable to connect both decap (of high frequency domains) and precision resistor GND points together. But if you have space constraints or other limitations you can do a star connection of these two nets to GND.

                 

                               Preferred location for Crystal is on the top plane near the pins (restrict Crystal traces to 10mm). You can place decaps on the bottom plane under the chip. For better understanding take a look at SuperSpeed Explorer kit HW files.

                 

               

                 

              Tnx