I use the GPIG II as the master mode to read a sram ,I use DR_ADDR and IN_DATA actions.I see the timing Simulation is wrong,whatever i do ,the data bus always end before address bus.The correct timing simulation is address bus should end before data buss,and when address bus is ended ,the data bus should hold more than 3ns.
I do not know where is wrong,plese refer me.
You have mentioned that the data bus be held for 3 nS than address bus. But in our documentation I do not find this timing requirement. There is no DATA-ADDR hold timing requirement.