8 Replies Latest reply on Nov 23, 2015 2:15 PM by cadi_1014291

    UDB Editor Example Project


      Hi all,


      Well that's it, had seen the UDB editor videos, and give it a try, so i find the UDB Editor info on Creator, at the end of the document is does a Step-By-Step project that takes a number, shift it twice to the left (aka multiply by 4) and add 127 to it, "very easy" i say.


      Did the Step-By-Step, and replace the LCD with an UART component to get the result of the operation, i feed the component with a decimal '10' value, i got a result of 0x28 (40) instead of 0xA7 (147) as expected, so i was not even able to make a Step-By-Step project run properly, by the result i guess the problem is on the add 127 instruction. Tried to fix the problem but i follow all the steps properly (i guess), i can't see the error,  maybe one of you can see it.


      Project is attached, i got it running on the 5LP Prototyping Kit, but it must run on any PSoC device.


      Thanks in advance



        • 1. Re: UDB Editor Example Project

          Your design isn't running because the "go" signal is connected to a constant 1 (logical high). So you cannot determine when a cycle has ended and a new cycle has to be started. You are reading intermediate results which will differ from the expected. I would suggest you to modify your state-machine or the go-signal accordingly. Solution could be to store result in F1 and read from there, it will not change until a new value is fed into A0-


          I modified your test-program to get more than only one value to compare several runs.





          • 2. Re: UDB Editor Example Project

            Hi Bob,


            I was checking when the state machine makes one cycle by toggling the 'done' signal on the last two states, then read that signal in the main design with the Status Register, the program stuck while the status register reads a '0' on that signal, when it read a '1' i print the results via UART.


            I did check your project but the component still making the math wrong, i think is a silly error i made on the datapath :/


            Thanks for the help, will post the project if i got it running properly.


            PD. the project is a example at the end of the UDB editor document




            Edit: I had edit the last step on the Datapath, now ALU = A1, A1 is where all the operations was going on, i get the expected result when i feed the component with a decimal '10', i got the result '0xA7' (decimal '167'), but when i feed another decimal value, let's say 5, i only got the multiplication by 4 result, so it's a little step closer to the desired functionality.


            Project is attached.



            • 3. Re: UDB Editor Example Project

              A step away from "wrong" might still be wrong  ;-)


              You do not stop your state-machine, it is running continously and so you're fetching intermediate results. Use the "go" input with a control register and wait until the signal has returned to zero in the last state. The math is quite ok, only the state-machine and its signals need some fixup.





              • 4. Re: UDB Editor Example Project

                As always you are right, i control the 'go' signal with a control register and it's working properly (my guess again), so why the cypress document uses a logic high controlling that signal? hard to guess. This is the working project so far.


                Thank you again Bob

                • 5. Re: UDB Editor Example Project

                  You might consider changing your project, but this would mean a jump into programming verilog yourself:


                  Interface changes:


                  Program writes into FiFo 0


                  Component calculates value (When FiFo not empty)


                  Component stores result into FiFo 1


                  Program checks for FiFo 1 not empty and reads off the result




                  Challenging, isn't it?



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                  • 6. Re: UDB Editor Example Project

                    Yes it is challenging since i have almost no experience programing Verilog, at the end of the UDB Editor Document also make this suggestion:


                    Additional projects:
                    If you successfully built and programmed this project, try a few other options to expand the design.
                    - Put the State Machine states to pins.
                    - Use the FIFOs.
                    - Make the "gain" of the block be programmable.
                    - Implement a PWM.


                    As first step i did try to change the last value added to the operation (the added '127'), i did it like this:


                    void `$INSTANCE_NAME`_SetAdition(uint8_t val){


                        CY_SET_REG8(`$INSTANCE_NAME`_Datapath_1_D0_PTR, val)






                    uint8_t `$INSTANCE_NAME`_GetAdition(void){


                        return CY_GET_REG8(`$INSTANCE_NAME`_Datapath_1_D0_PTR)






                    Seems like it's working. I think datapath edition it's what makes PSoC really unique from the other microcontrollers, what do you think?, but i had not found a lot much information about it, or i'm searching it wrong, i saw PSoC Today episodes about Datapath and DMA with David and Todd, i was amazed.


                    Thanks for the help and challenges.





                    1 of 1 people found this helpful
                    • 7. Re: UDB Editor Example Project

                      Carlos, I do not know what your primary business is, but having any experience with a HDL like verilog will always look good in a résumé.





                      • 8. Re: UDB Editor Example Project

                        I'm a student, so still a lot of  learn :D. Will post my progress and made more questions about datapath if you don't mind.


                        (until the release of PSoC4-L)