4 Replies Latest reply on Dec 2, 2015 12:53 PM by cadi_1014291

    ADC DelSig Interrupt Routines, IRQ and INT


      Hi all,


      I have a maybe n00b question, but i found 2 files with interrupt functions for this ADC:


      The files are:








      i tried to search differences between those but the comments on the files doesn't help me a lot.


      When should i use one or the other?


      ADC_DelSig_INT have 4 function Callbacks, those are ADC_DelSig_ISR1 trough ADC_DelSig_ISR4


      Where can i find more information about this functions and when to use them? Are those specific for each resolution of the ADC or maybe the number of channels?




      Any info is appreciated





        • 1. Re: ADC DelSig Interrupt Routines, IRQ and INT

          Those four callbacks are for the possible different configurations of the ADC. One callback for each.





          • 2. Re: ADC DelSig Interrupt Routines, IRQ and INT

            Thanks for the help Bob, i found the info about it on the component datasheet after seeing your reply. Silly me for don't read the entire datasheet.


            Thanks again



            • 3. Re: ADC DelSig Interrupt Routines, IRQ and INT

              In my opinion Cypress has got outstanding good datasheets (at least after some corrections) and the datasheet for a component is always just a mouse click away. Furthermore Cypress provided us with the Document Manager which allows for searching and finding documentation, too rarely used, but quite helpful!





              • 4. Re: ADC DelSig Interrupt Routines, IRQ and INT

                I had still reading SAR ADC documentation, now i had read the PSoC 5LP Architecture TRM Rev *C, page 388, 38.2.3 Input Sampling section, it says the input sampling time can be programmed from 1 to 64 cycles in register SARx_CSR2[5:0] register bits, so i make a simple project where the ADC is configured to 8bit resolution, continuous sampling, i enable the EoS output and attach a digital output to it, also another to the EoC output and another one to the external clock that is feeding the ADC (1MHz clock), then i debug the component and SARx_CSR2 = 0x0440, this means the sampling time is 4 clock cycles and 8bit resolution.


                Later after the same section says: "The conversion time is 18 cycles for input sampling time up to four cycles.", but i see only 14 clock cycles when i plug a logic analyzer to the output, attached are two images that almost explain this. The project just configures the ADC.


                Any idea on why i see 14 instead of 18 clock cycles? the logic analyzer trigger is tricking me again?




                Thanks in advance